Estimation and Partitioning for CPU-Accelerator Architectures

We developed an approach for studying the design space when interfacing reconfigurable accelerators with a CPU. We consider reconfigurable accelerators that are controlled by a CPU via a direct low-latency interface but also have direct access to the memory hierarchy. In order to investigate those, we present a framework based on the LLVM infrastructure that performs estimation of the runtime on the target architecture utilizing profiling information and code analysis. It finds the optimal hardware/software partitioning by forming a corresponding ILP problem. The process is fully automated and enables the evaluation of various architecture parameters.