A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs

A quad high-speed transceiver cell is designed and implemented in 0.13 /spl mu/m CMOS technology. To achieve low jitter while maintaining low power consumption, dual on-chip regulators are used for each dual-loop PLL. The prototype chip demonstrates that the links can operate from 400 Mb/s to 4 Gb/s with a bit error rate <10/sup -14/. The quad cell consumes 390 mW at 2.5 Gb/s (95 mW/link) under typical operating conditions with a 400 mV output swing driving double terminated links.

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