Toward a pixel-parallel architecture for graph cuts inference on FPGA
暂无分享,去创建一个
[1] Vladimir Kolmogorov,et al. An Experimental Comparison of Min-Cut/Max-Flow Algorithms for Energy Minimization in Vision , 2004, IEEE Trans. Pattern Anal. Mach. Intell..
[2] P. J. Narayanan,et al. CUDA cuts: Fast graph cuts on the GPU , 2008, 2008 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops.
[3] Tsutomu Maruyama,et al. An acceleration of a graph cut segmentation with FPGA , 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).
[4] Andrew V. Goldberg,et al. On Implementing the Push—Relabel Method for the Maximum Flow Problem , 1997, Algorithmica.
[5] William Thomas Blank. A bit map architecture and algorithms for design automation , 1982 .
[6] Richard Szeliski,et al. A Comparative Study of Energy Minimization Methods for Markov Random Fields with Smoothness-Based Priors , 2008, IEEE Transactions on Pattern Analysis and Machine Intelligence.
[7] Ioannis Papaefstathiou,et al. Highly efficient reconfigurable parallel graph cuts for embedded vision , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[8] Rob A. Rutenbar,et al. Video-Rate Stereo Matching Using Markov Random Field TRW-S Inference on a Hybrid CPU+FPGA Computing Platform , 2016, IEEE Transactions on Circuits and Systems for Video Technology.
[9] Olga Veksler,et al. Fast Approximate Energy Minimization via Graph Cuts , 2001, IEEE Trans. Pattern Anal. Mach. Intell..