Synthesis of low power folded programmable coefficient FIR digital filters

A novel low-power synthesis technique is presented for the design of folded or time-multiplexed programmable-coefficient FIR filters where storage area is traded-off for lowering power consumption. A systematic technique is developed for low power mapping of FIR filters to architectures with arbitrary number of multipliers and adders. Power consumed in multipliers is reduced by reducing switching activity at both the data-in as well as the coefficient input. Common input operands can be exposed unfolding, which, however leads to a memory Increase. Simulation are obtained for folding 65 and 129 tap bandpass FIR filters. The average power consumed in a multiplier for a fixed number of hardware multipliers with varying unfolding factors is compared. It is observed that most of the gains due to unfolding are obtained for relatively small unfolding factors and therefore for relatively small memory area overhead. Depending on the unfolding factor employed the average power consumed in a multiplier is seen to reduce anywhere from 54.75% to 81.73% when transpose FIR filters are synthesized as opposed to synthesizing direct-form FIR filters with no unfolding.

[1]  Keshab K. Parhi,et al.  Synthesis of control circuits in folded pipelined DSP architectures , 1992 .

[2]  David P. Williamson,et al.  A general approximation technique for constrained forest problems , 1992, SODA '92.

[3]  Joos Vandewalle,et al.  An efficient microcode compiler for application specific DSP processors , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Keshab K. Parhi,et al.  Synthesis of folded pipelined architectures for multirate DSP algorithms , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Keshab K. Parhi,et al.  HEAT: hierarchical energy analysis tool , 1996, DAC '96.

[6]  Charles E. Leiserson,et al.  Optimizing synchronous systems , 1981, 22nd Annual Symposium on Foundations of Computer Science (sfcs 1981).

[7]  Niraj K. Jha,et al.  Behavioral synthesis for low power , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[8]  Anantha P. Chandrakasan,et al.  Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.

[9]  R. Mehra,et al.  Exploiting locality for low-power design , 1996, Proceedings of Custom Integrated Circuits Conference.

[10]  Alan V. Oppenheim,et al.  Discrete-Time Signal Pro-cessing , 1989 .

[11]  Thanos Stouraitis,et al.  A novel methodology for power consumption reduction in a class of DSP algorithms , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[12]  Keshab K. Parhi,et al.  Synthesis of folded, pipelined architectures for multi-dimensional multirate systems , 1998, Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181).

[13]  Keshab K. Parhi,et al.  Systematic synthesis of DSP data format converters using life-time analysis and forward-backward register allocation , 1992 .

[14]  Keshab K. Parhi,et al.  Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding , 1991, IEEE Trans. Computers.

[15]  Miodrag Potkonjak,et al.  Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Tughrul Arslan,et al.  Data block processing for low power implementation of direct form FIR filters on single multiplier CMOS DSPs , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[17]  Jan M. Rabaey,et al.  Exploiting regularity for low-power design , 1996, Proceedings of International Conference on Computer Aided Design.

[18]  Jan M. Rabaey,et al.  Low-power architectural synthesis and the impact of exploiting locality , 1996, J. VLSI Signal Process..

[19]  Keshab K. Parhi,et al.  Synthesis of folded multi-dimensional DSP systems , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).