SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts

Recent advances in process technology have resulted in novel defect mechanisms making the test generation process very challenging. In addition to complete opens and shorts that can be represented via extreme defect resistance magnitudes, partial resistive opens and shorts are also of concern in deeply scaled CMOS technologies. For open defects with intermediate defect magnitude values, it has been shown that multi-pattern tests are necessary for defect exposure. We extend this approach to short defects with intermediate defect magnitude values to obtain a suite of multi-pattern tests for standard cell instances that cover complete as well as partial intra-cell open and short defects. A hierarchical scan-compatible SAT-based test generation approach for full scan sequential circuits is then proposed that allows such multi-pattern tests to be applied to the circuit via the scan infrastructure. A key innovation is the combined use of shift and capture operations along with launch-on-capture and launch-on-shift scan based test application for increased defect coverage. Resulting defect coverage improvements over conventional two-pattern tests are demonstrated on ISCAS89 benchmark circuits.

[1]  Jerry Soden,et al.  Test Considerations for Gate Oxide Shorts in CMOS ICs , 1986, IEEE Design & Test of Computers.

[2]  Rolf Drechsler,et al.  Speeding up SAT-Based ATPG Using Dynamic Clause Activation , 2009, 2009 Asian Test Symposium.

[3]  M. Renovell,et al.  Delta-IDDQ Testing of Resistive Short Defects , 2006, 2006 15th Asian Test Symposium.

[4]  Rolf Drechsler,et al.  Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization , 2014, 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

[5]  Friedrich Hapke,et al.  Cell-aware Production test results from a 32-nm notebook processor , 2012, 2012 IEEE International Test Conference.

[6]  A. Jee,et al.  An analysis of shorts in CMOS standard cell circuits , 1994, Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit.

[7]  Rolf Drechsler,et al.  A Highly Fault-Efficient SAT-Based ATPG Flow , 2012, IEEE Design & Test of Computers.

[8]  Mark Mohammad Tehranipoor,et al.  Circuit Topology-Based Test Pattern Generation for Small-Delay Defects , 2010, 2010 19th IEEE Asian Test Symposium.

[9]  Rolf Drechsler,et al.  Incremental Solving Techniques for SAT-based ATPG , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Ke Peng,et al.  Challenges in Cell-Aware Test , 2018, 2018 IEEE 23rd European Test Symposium (ETS).

[11]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[12]  Edward J. McCluskey,et al.  "RESISTIVE SHORTS" WITHIN CMOS GATES , 1991, 1991, Proceedings. International Test Conference.

[13]  Jacob A. Abraham,et al.  Characterization and Testing of Physical Failures in MOS Logic Circuits , 1984, IEEE Design & Test of Computers.

[14]  Daniel Arumí,et al.  Experimental Characterization of CMOS Interconnect Open Defects , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Rolf Drechsler,et al.  PASSAT: efficient SAT-based test pattern generation for industrial circuits , 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

[16]  Amit Karel,et al.  Influence of Body-Biasing, Supply Voltage, and Temperature on the Detection of Resistive Short Defects in FDSOI Technology , 2017, IEEE Transactions on Nanotechnology.

[17]  Edward J. McCluskey,et al.  Detecting resistive shorts for CMOS domino circuits , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[18]  Abhijit Chatterjee,et al.  Characterization of Library Cells for Open-circuit Defect Exposure: A Systematic Methodology , 2019, 2019 IEEE International Test Conference (ITC).

[19]  Tracy Larrabee,et al.  Test pattern generation using Boolean satisfiability , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Friedrich Hapke,et al.  Cell-Aware Test , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  E.J. McCluskey,et al.  Detecting bridging faults in dynamic CMOS circuits , 1997, Digest of Papers IEEE International Workshop on IDDQ Testing.

[22]  Robert K. Brayton,et al.  Combinational test generation using satisfiability , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  A. Chehab,et al.  Transient Current Testing of Gate-Oxide Shorts in CMOS , 2007, 2007 2nd International Design and Test Workshop.

[24]  Edward J. McCluskey,et al.  Gate exhaustive testing , 2005, IEEE International Conference on Test, 2005..