An analog VLSI architecture for auditory based feature extraction

We have developed a low power analog VLSI chip for real time signal processing motivated by the principles of the human auditory system. An analog cochlear filter bank (which is implemented on the chip) decomposes the input audio signal into several frequency bands that have almost equal bandwidth on a log scale. This step is thus similar to computing the wavelet transform. The chip then computes signal energies and zero crossing time intervals of frequency components in a cochlear filter bank. The chip is intended to work as a front-end of a speech recognition system. We include experimental results on a VLSI implementation of the auditory front-end. We present speech recognition results on the TI-DIGITS database obtained from computer simulations which model the functionality of the feature extraction VLSI hardware. We use hidden Markov models (HMM) in combination with linear discriminant analysis (LDA) for the recognizer design.

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