Design of Energy Efficient Digital Circuits

Recent technology advances have resulted in power being the major concern for digital design. In this chapter we address how transistor sizing affects the energy and delay of digital circuits. The state of the art in circuit design methodology (Logical Effort) is examined and we identify its limitations for design in the energy-delay space. We examine how to explore the entire energy-delay space for a circuit and present an approach for the design and analysis in the energy-delay space which allows for energy reduction without performance penalty. Finally, we present techniques for the design of energy-efficient digital circuits.

[1]  Mark Horowitz,et al.  Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  John P. Fishburn,et al.  TILOS: A posynomial programming approach to transistor sizing , 2003, ICCAD 2003.

[3]  Keshab K. Parhi,et al.  Fast and exact transistor sizing based on iterative relaxation , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Mark Horowitz,et al.  Timing Models for MOS Circuits , 1983 .

[5]  Harold S. Stone,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.

[6]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[7]  Sanu Mathew,et al.  Comparison of high-performance VLSI adders in the energy-delay space , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .

[9]  B. S. Meyerson.  Opening Keynote Address - How does one define "technology" now that classical scaling is dead (and has been for years)? , 2005, DAC 2005.

[10]  V.G. Oklobdzija,et al.  Energy minimization method for optimal energy-delay extraction , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

[11]  Bart R. Zeydel,et al.  Energy optimization of pipelined digital systems using circuit sizing and supply scaling , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Yuan Taur,et al.  CMOS design near the limit of scaling , 2002 .

[13]  Vojin G. Oklobdzija,et al.  On Implementing Addition in VLSI Technology , 1988, J. Parallel Distributed Comput..

[14]  Ivan E. Sutherland,et al.  Logical effort: designing for speed on the back of an envelope , 1991 .

[15]  Victor V. Zyuban,et al.  Balancing hardware intensity in microprocessor pipelines , 2003, IBM J. Res. Dev..

[16]  Stephen P. Boyd,et al.  Convex Optimization , 2004, Algorithms and Theory of Computation Handbook.

[17]  R.W. Brodersen,et al.  Energy–delay tradeoffs in combinational logic using gate sizing and supply voltage optimization , 2002, Proceedings of the 28th European Solid-State Circuits Conference.

[18]  Kjell O. Jeppson,et al.  CMOS Circuit Speed and Buffer Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  R.W. Brodersen,et al.  Methods for true energy-performance optimization , 2004, IEEE Journal of Solid-State Circuits.

[20]  V. Zyuban,et al.  Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels , 2002, Proceedings of the International Symposium on Low Power Electronics and Design.

[21]  H. Peter Hofstee.  Power-constrained microprocessor design , 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.