The impact of intrinsic device fluctuations on CMOS SRAM cell stability
暂无分享,去创建一个
[1] James D. Meindl,et al. Dynamic-threshold CMOS SRAM cells for fast, portable applications , 2000, Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541).
[2] Keith A. Bowman,et al. A minimum total power methodology for projecting limits on CMOS GSI , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[3] J. Meindl,et al. A physical alpha-power law MOSFET model , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).
[4] J.D. Meindl,et al. MOSFET Fluctuation Limits on Gigascale Integration (GSI) , 1998, 28th European Solid-State Device Research Conference.
[5] Vivek De,et al. Intrinsic MOSFET parameter fluctuations due to random dopant placement , 1997, IEEE Trans. Very Large Scale Integr. Syst..
[6] D. Burnett,et al. Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits , 1994, Proceedings of 1994 VLSI Technology Symposium.
[7] James D. Meindl,et al. Opportunities for Scaling FET's for Gigascale Integration (GSI) , 1993, ESSDERC '93: 23rd European solid State Device Research Conference.
[8] T. Mizuno,et al. Experimental Study Of Threshold Voltage Fluctuations Using An 8k MOSFET's Array , 1993, Symposium 1993 on VLSI Technology.
[9] E. Seevinck,et al. Static-noise margin analysis of MOS SRAM cells , 1987 .
[10] J. Lohstroh,et al. Worst-case static noise margin criteria for logic circuits and their mathematical equivalence , 1983, IEEE Journal of Solid-State Circuits.
[11] R. Keyes. The effect of randomness in the distribution of impurity atoms on FET thresholds , 1975 .