Sulfur-Induced PtSi:C/Si:C Schottky Barrier Height Lowering for Realizing N-Channel FinFETs With Reduced External Resistance

In this letter, sulfur (S) segregation was exploited to attain a record-low electron barrier height (PhiB N) of 110 meV for platinum-based silicide contacts. Sulfur-incorporated PtSi:C/Si:C contacts were also demonstrated in strained FinFETs with Si:C source/drain stressors. Incorporation of sulfur at the PtSi:C/Si:C interface in the source/drain regions of FinFETs provides a 51% improvement in external resistances and a 45% enhancement in drive current as compared to devices without S segregation. The remarkable reduction in PhiB N is explained using charge transfer and dipole formation at the silicide/semiconductor interface with S segregation.

[1]  Guo-Qiang Lo,et al.  Novel and cost-efficient single metallic silicide integration solution with dual Schottky-barrier achieved by aluminum inter-diffusion for FinFET CMOS technology with enhanced performance , 2008, 2008 Symposium on VLSI Technology.

[2]  Scheffler,et al.  Formation energies, electronic structure, and hyperfine fields of chalcogen point defects and defect pairs in silicon. , 1991, Physical review. B, Condensed matter.

[3]  N. Taoka,et al.  Modulation of NiGe∕Ge Schottky barrier height by sulfur segregation during Ni germanidation , 2006 .

[4]  Wen-Chin Lee,et al.  Manufacturable Processes for $\leq$ 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances , 2008, IEEE Transactions on Electron Devices.

[5]  Qing-Tai Zhao,et al.  Tuning of NiSi/Si Schottky barrier heights by sulfur segregation during Ni silicidation , 2005 .

[6]  N. Collaert,et al.  Analysis of the parasitic S/D resistance in multiple-gate FETs , 2005, IEEE Transactions on Electron Devices.

[7]  Jerry Tersoff,et al.  Theory of semiconductor heterojunctions: The role of quantum dipoles , 1984 .

[8]  Carlton M. Osburn,et al.  Low parasitic resistance contacts for scaled ULSI devices , 1998 .

[9]  S. Narasimha,et al.  (110) channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (Rext) engineering , 2007, 2007 IEEE International Electron Devices Meeting.

[10]  G. Lo,et al.  Nickel-Silicide:Carbon Contact Technology for N-Channel MOSFETs With Silicon–Carbon Source/Drain , 2008, IEEE Electron Device Letters.