VERILAT: verification using logic augmentation and transformations

This paper presents a new framework for formal logic verification. What is depicted here is fundamentally different from previous approaches. In earlier approaches, the circuit is either not changed during the verification process, as in OBDD or implication-based methods, or the circuit is progressively reduced during verification. Whereas in our approach, we actually enlarge the circuits by adding gates during the verification process. Specifically introduced here is a new technique that transforms the reference circuit as well as the circuit to be verified, so that the similarity between the two is progressively enhanced. This requires addition of gates to the reference circuit and/or the circuit to be verified. In the process, we reduce the dissimilarity between the two circuits, which makes it easier to verify the circuits.

[1]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[2]  Kwang-Ting Cheng,et al.  Combinational and sequential logic optimization by redundancy addition and removal , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Dhiraj K. Pradhan,et al.  LOT: Logic optimization with testability - new transformations using recursive learning , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[4]  D. Brand.  Verification of large synthesized designs , 1993, ICCAD 1993.

[5]  Albert R. Wang,et al.  Logic verification using binary decision diagrams in a logic synthesis environment , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[6]  Dhiraj K. Pradhan,et al.  Functional learning: a new approach to learning in digital circuits , 1994, Proceedings of IEEE VLSI Test Symposium.

[7]  Dhiraj K. Pradhan,et al.  A novel framework for logic verification in a synthesis environment , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Yusuke Matsunaga.  An efficient equivalence checker for combinational circuits , 1996, DAC '96.

[9]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[10]  Wolfgang Kunz,et al.  HANNIBAL: An efficient tool for logic verification based on recursive learning , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[11]  Andreas Kuehlmann,et al.  Equivalence checking using cuts and heaps , 1997, DAC.

[12]  Randal E. Bryant,et al.  Verification of Arithmetic Circuits with Binary Moment Diagrams , 1995, 32nd Design Automation Conference.

[13]  Premachandran R. Menon,et al.  Multi-level Logic Optimization By Implication Analysis , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[14]  Randal E. Bryant,et al.  Efficient implementation of a BDD package , 1991, DAC '90.

[15]  Dhiraj K. Pradhan,et al.  Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization , 1994, The IEEE International Symposium on Circuits and Systems, 2003. Tutorial Guide: ISCAS 2003..

[16]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.