Approximation of Worst-Case Execution Time for Preemptive Multitasking Systems

The control system of many complex mechatronic products requires for each task the Worst Case Execution Time (WCET), which is needed for the scheduler's admission tests and subsequently limits a task's execution time during operation. If a task exceeds the WCET, this situation is detected and either a handler is invoked or control is transferred to a human operator. Such control systems usually support preemptive multitasking, and if an object-oriented programming language (e.g., Java, C++, Oberon) is used, then the system may also provide dynamic loading and unloading of software components (modules). Only modern, state-of-the art microprocessors can provide the necessary compute cycles, but this combination of features (preemption, dynamic un/loading of modules, advanced processors) creates unique challenges when estimating the WCET. Preemption makes it difficult to take the state of the caches and pipelines into account when determining the WCET, yet for modern processors, a WCET based on worst-case assumptions about caches and pipelines is too large to be useful, especially for big and complex real-time products. Since modules can be loaded and unloaded, each task must be analyzed in isolation, without explicit reference to other tasks that may execute concurrently. To obtain a realistic estimate of a task's execution time, we use static analysis of the source code combined with information about the task's runtime behavior. Runtime information is gathered by the performance monitor that is included in the processor's hardware implementation. Our predictor is able to compute a good estimation of the WCET even for complex tasks that contain a lot of dynamic cache usage, and its requirements are met by today's performance monitoring hardware. The paper includes data to evaluate the effectiveness of the proposed technique for a number of robotics control kernels that are written in an object-oriented programming language and execute on a PowerPC 604e-based system.

[1]  David B. Whalley,et al.  Bounding loop iterations for timing analysis , 1998, Proceedings. Fourth IEEE Real-Time Technology and Applications Symposium (Cat. No.98TB100245).

[2]  Sang Lyul Min,et al.  Efficient worst case timing analysis of data caching , 1996, Proceedings Real-Time Technology and Applications.

[3]  Philip G. Emma,et al.  Understanding some simple processor-performance limits , 1997, IBM J. Res. Dev..

[4]  Hanspeter Mössenböck,et al.  The Programming Language Oberon-2 , 1991, Struct. Program..

[5]  Guangtian Liu,et al.  Efficient Run-time Monitoring Of Timing Constraints , 1997, Proceedings Third IEEE Real-Time Technology and Applications Symposium.

[6]  Joachim Wegener,et al.  A Comparison of Static Analysis and Evolutionary Testing for the Verification of Timing Constraints , 1998, Proceedings. Fourth IEEE Real-Time Technology and Applications Symposium (Cat. No.98TB100245).

[7]  Friedhelm Stappert,et al.  Complete worst-case execution time analysis of straight-line hard real-time programs , 2000, J. Syst. Archit..

[8]  Sharad Malik,et al.  Cache modeling for real-time software: beyond direct mapped instruction caches , 1996, 17th IEEE Real-Time Systems Symposium.

[9]  Steven S. Muchnick,et al.  Advanced Compiler Design and Implementation , 1997 .

[10]  Peter Altenbernd,et al.  On the false path problem in hard real-time programs , 1996, Proceedings of the Eighth Euromicro Workshop on Real-Time Systems.

[11]  Sang Lyul Min,et al.  Analysis of cache-related preemption delay in fixed-priority preemptive scheduling , 1998, 17th IEEE Real-Time Systems Symposium.

[12]  A. D. Stoyenko,et al.  Real-time Euclid: a language for reliable real-time systems , 1989 .

[13]  Jochen Liedtke,et al.  OS-controlled cache predictability for real-time systems , 1997, Proceedings Third IEEE Real-Time Technology and Applications Symposium.

[14]  David B. Whalley,et al.  Bounding Pipeline and Instruction Cache Performance , 1999, IEEE Trans. Computers.

[15]  Chang-Gun Lee,et al.  Enhanced analysis of cache-related preemption delay in fixed-priority preemptive scheduling , 1996, Proceedings Real-Time Systems Symposium.

[16]  Henrik Theiling,et al.  Combining abstract interpretation and ILP for microarchitecture modelling and program path analysis , 1998, Proceedings 19th IEEE Real-Time Systems Symposium (Cat. No.98CB36279).

[17]  Alexander D. Stoyen,et al.  Real-Time Euclid: A language for reliable real-time systems , 1989, IEEE Transactions on Software Engineering.

[18]  Andy J. Wellings,et al.  Adding instruction cache effect to an exact schedulability analysis of preemptive real-time systems , 1996, Proceedings of the Eighth Euromicro Workshop on Real-Time Systems.

[19]  Peter P. Puschner,et al.  Problems in Static Worst-Case Execution Time Analysis , 1997, MMB.

[20]  Sang Lyul Min,et al.  A worst case timing analysis technique for multiple-issue machines , 1998, Proceedings 19th IEEE Real-Time Systems Symposium (Cat. No.98CB36279).

[21]  Charles P. Roth,et al.  A programmer's view of performance monitoring in the PowerPC microprocessor , 1997, IBM J. Res. Dev..

[22]  D. B. Kirk,et al.  SMART (strategic memory allocation for real-time) cache design , 1989, [1989] Proceedings. Real-Time Systems Symposium.

[23]  Peter P. Puschner,et al.  Testing the results of static worst-case execution-time analysis , 1998, Proceedings 19th IEEE Real-Time Systems Symposium (Cat. No.98CB36279).

[24]  Niklaus Wirth,et al.  Project Oberon - the design of an operating system and compiler , 1992 .

[25]  Sang Lyul Min,et al.  An Accurate Worst Case Timing Analysis for RISC Processors , 1995, IEEE Trans. Software Eng..

[26]  Sheng Cheng,et al.  Scheduling algorithms for hard real-time systems: a brief survey , 1989 .

[27]  Andy J. Wellings,et al.  Adding instruction cache effect to schedulability analysis of preemptive real-time systems , 1996, Proceedings Real-Time Technology and Applications.

[28]  David B. Whalley,et al.  Tighter timing predictions by automatic detection and exploitation of value-dependent constraints , 1999, Proceedings of the Fifth IEEE Real-Time Technology and Applications Symposium.

[29]  Kenneth E. Iverson,et al.  A programming language , 1899, AIEE-IRE '62 (Spring).

[30]  David B. Whalley,et al.  Supporting the specification and analysis of timing constraints , 1996, Proceedings Real-Time Technology and Applications.

[31]  Roberto Brega,et al.  A REAL-TIME OPERATING SYSTEM DESIGNED FOR PREDICTABILITY AND RUN-TIME SAFETY , 1998 .

[32]  Jeffrey Dean,et al.  ProfileMe: hardware support for instruction-level profiling on out-of-order processors , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[33]  Roberto Brega,et al.  Application of a nonlinear adaptive controller to a 6 DOF parallel manipulator , 2000, Proceedings 2000 ICRA. Millennium Conference. IEEE International Conference on Robotics and Automation. Symposia Proceedings (Cat. No.00CH37065).