A Low-Power Block-Matching Cell for Video Compression

AbstractThis paper describes theimplementation of a block-matching modulewith digital I/O. Algorithmic analysisdemonstrates that the precisionrequirements can be met by a compactcircuit that processes the signal in thecharge domain. The required conversionbetween voltages and charges is achieved byMOS capacitors. As a result, it can befabricated by any inexpensive digital CMOStechnology. A test chip has beenimplemented in a standard CMOS 1.6 μmtechnology and the measured energyconsumption is 1.2 nJ per block match usingan $$8 \times 8$$ pixel matrix. Simulations ofthe same cell in 0.35 μm and 0.25 μmCMOS technology are presented, showing thescalability of the approach.

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