Research on a chip scale atomic clock aided vector tracking loop

With the development of Micro-Electro-Mechanical-System (MEMS) technology, size and accuracy of Chip Scale Atomic Clock (CSAC) gradually improve, and a commercial CSAC products available, which makes it possible to integrate a CSAC to a handheld GNSS receiver. Published results have demonstrated that CSAC could better the Scalar Tracking Loops (STL) navigation results. However, the Vector Tracking Loop (VTL) has a different architecture compared with STL, which allows it meaningful to investigate CSAC driven VTL. In this study, two problems are discussed in a classic VTL employing CSAC as frequency reference: (i) how much improvement in navigation solutions initialed by substituting TXCO with CASC; (ii) whether the CSAC driven VTL can work excluding clock bias or clock drift as state variables, in other words, whether the VTL can provide navigation solutions at a moderate accuracy with only three satellites in view. Two comparisons have been done in this investigation and demonstrated that CSAC could improve the VTL navigation solutions, and the clock drift variable could be removed from the VTL model with no influence on the VTL performance.