SOI MOSFETs are susceptible to the local thermal heating generated in the channel due to the lesser thermal conductivity of their buried oxide. Even with a /spl sim/100 nm thin buried oxide, SOI MOSFET DC I-V characteristics, from which SPICE parameters are extracted, show current loss due to the self-heating. On the other hand, for most logic circuits in an LSI, the self-heating effect is insignificant. Since the average power per device is low and the switching time (/spl sim/10 ps) is much shorter than the thermal constant (/spl sim/100 ns), the device temperature increase due to the self-heating is quite small. Therefore, for an accurate circuit design, we must correct the DC I-V data for the self-heating. In this paper, the thermal dissipation paths in SOI MOSFETs are investigated via experiments and modeling.