A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18 /spl mu/m CMOS technology

Two architectures for a 1-V, 10-bit 200-kS/s successive approximation analog-to-digital converter (ADC) implemented in a standard CMOS 0.18 /spl mu/m digital process are presented. A track-and-hold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch with a novel rail-to-rail track-and-latch comparator circuit is described. A pMOS-only ladder containing a rail-to-rail current-to-voltage converter, performs the DAC function in the second ADC topology whereas a conventional R-2R ladder is used in the first one. Successive approximation and control logic is implemented using of robust single clock phase D flip flop.

[1]  Qiuting Huang,et al.  Design and implementation of an untrimmed MOSFET-only 10-bit A/D converter with -79-dB THD , 1998 .

[2]  J. A. Connelly,et al.  An analysis methodology to identify dominant noise sources in D/A and A/D converters , 1991 .

[3]  A. Yukawa,et al.  A CMOS 8-Bit High-Speed A/D Converter IC , 1984, IEEE Journal of Solid-State Circuits.

[4]  H. Samavati,et al.  Fractal capacitors , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[5]  W. Sansen,et al.  A 900-mV low-power ΔΣ A/D converter with 77-dB dynamic range , 1998, IEEE J. Solid State Circuits.

[6]  P. R. Gray,et al.  A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter , 1999, IEEE J. Solid State Circuits.

[7]  G. Geelen,et al.  An inherently linear and compact MOST-only current division technique , 1992 .

[8]  Gordon W. Roberts,et al.  On-chip analog signal generation for mixed-signal built-in self-test , 1999 .

[9]  M. Afghahi.  A robust single phase clocking for low power, high-speed VLSI applications , 1996 .

[10]  Mohamad Sawan,et al.  Low power/low voltage high speed CMOS differential track and latch comparator with rail-to-rail input , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[11]  M. Sawan,et al.  Low-voltage CMOS analog switch for high precision sample-and-hold circuit , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[12]  Michael Peter Kennedy.  On the robustness of R-2R ladder DACs , 2000 .

[13]  E.K.F. Lee,et al.  A 1-V, 8-bit successive approximation ADC in standard CMOS process , 2000, IEEE Journal of Solid-State Circuits.

[14]  Y. Matsuya,et al.  1V power supply, 384 ks/s 10b A/D and D/A converters with swing-suppression noise shaping , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.