A fast and accurate delay dependent method for switching estimation of large combinational circuits

Assuming inertial gate delay model, the first-order temporal correlation and the structural dependencies, a probabilistic method to estimate the switching activity of a combinational circuit, is introduced. To capture the first temporal correlation a novel mathematical model and the associated new formulas are derived. Also, a modified boolean function, which describes the logic and timing behavior of each signal, is introduced. To capture the structural dependencies an efficient new method to partition a large circuit into small independent sub-circuits is proposed. Finally, an algorithm that evaluates the switching activity of any circuit node is presented.

[1]  Sarma B. K. Vrudhula,et al.  A Technique for Estimating Signal Activity in Logic Circuits , 1998, Integr. Comput. Aided Eng..

[2]  Ibrahim N. Hajj,et al.  Probabilistic simulation for reliability analysis of CMOS VLSI circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Edward J. McCluskey,et al.  Probabilistic Treatment of General Combinational Networks , 1975, IEEE Transactions on Computers.

[4]  José C. Monteiro,et al.  Switching activity estimation using limited depth reconvergent path analysis , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[5]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[6]  Farid N. Najm,et al.  A survey of power estimation techniques in VLSI circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[7]  Massoud Pedram,et al.  Low power design methodologies , 1996 .

[8]  Athanasios Papoulis,et al.  Probability, Random Variables and Stochastic Processes , 1965 .

[9]  Bhanu Kapoor Improving the Accuracy of Circuit Activity Measurement , 1994, 31st Design Automation Conference.

[10]  Chi-Ying Tsui,et al.  Gate-level power estimation using tagged probabilistic simulation , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Kurt Keutzer,et al.  Estimation of average switching activity in combinational logic circuits using symbolic simulation , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Radu Marculescu,et al.  Probabilistic modeling of dependencies during switching activity analysis , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Ulf Schlichtmann,et al.  Fast Power Estimation of Large Circuits , 1996, IEEE Des. Test Comput..

[14]  Farid N. Najm,et al.  Transition density: a new measure of activity in digital circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..