On circuit techniques to improve noise immunity of CMOS dynamic logic

Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology. In the literature, a number of design techniques have been proposed to enhance the noise tolerance of dynamic logic gates. An overview and classification of these techniques are first presented in this paper. Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained. Simulation results on large fan-in dynamic CMOS logic gates have shown that, at a supply voltage of 1.6 V, the input noise immunity level can be increased to 0.8 V for about 10% delay overhead and to 1.0 V for only about 20% delay overhead.

[1]  Atila Alvandpour,et al.  A sub-130-nm conditional keeper technique , 2002, IEEE J. Solid State Circuits.

[2]  Christer Svensson,et al.  Noise in digital dynamic CMOS circuits , 1994 .

[3]  Chung-Yu Wu,et al.  The new general realization theory of FET-like integrated voltage-controlled negative differential resistance devices , 1981 .

[4]  Vojin G. Oklobdzija,et al.  Design-performance trade-offs in CMOS-domino logic , 1986 .

[5]  T. Yamauchi,et al.  2.5V Novel CMOS Circuit Techniques for a 150MHz Superscalar RISC Processor , 1995, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.

[6]  Ibrahim N. Hajj,et al.  Design of dynamic circuits with enhanced noise tolerance , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

[7]  Pinaki Mazumder,et al.  Device and circuit simulation of quantum electronic devices , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Koichi Maezawa,et al.  A novel ultrafast functional device: resonant tunneling high electron mobility transistor , 1996, Proceedings 1996 IEEE Hong Kong Electron Devices Meeting.

[9]  Kwok K. Ng.  A survey of semiconductor devices , 1996 .

[10]  C. M. Lee,et al.  High-speed compact circuits with CMOS , 1982 .

[11]  Mohamed I. Elmasry,et al.  High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[12]  Leon O. Chua,et al.  Bipolar - JFET - MOSFET negative resistance devices , 1985 .

[13]  D. Auvergne,et al.  A comprehensive delay macro modeling for submicrometer CMOS logics , 1999, IEEE J. Solid State Circuits.

[14]  Pinaki Mazumder,et al.  Digital circuit applications of resonant tunneling devices , 1998, Proc. IEEE.

[15]  Mohamed I. Elmasry,et al.  Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[16]  Fumio Murabayashi,et al.  2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor , 1996 .

[17]  Cy Wu,et al.  INTEGRATED ALPHA-TYPE DIFFERENTIAL NEGATIVE-RESISTANCE MOSFET DEVICE , 1979 .

[18]  Naresh R. Shanbhag,et al.  The twin-transistor noise-tolerant dynamic circuit technique , 2001, IEEE J. Solid State Circuits.

[19]  K. M. Indlekofer,et al.  A vertical resonant tunneling transistor for application in digital logic circuits , 2001 .

[20]  L. Heller,et al.  Cascode voltage switch logic: A differential CMOS logic family , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[21]  Kenneth L. Shepard,et al.  Noise in deep submicron digital design , 1996, Proceedings of International Conference on Computer Aided Design.

[22]  Naresh R. Shanbhag,et al.  Noise-tolerant dynamic circuit design , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[23]  C. M. Lee,et al.  Zipper CMOS , 1986, IEEE Circuits and Devices Magazine.

[24]  Naresh R. Shanbhag,et al.  An energy-efficient noise-tolerant dynamic circuit technique , 2000 .

[25]  Naresh R. Shanbhag,et al.  Energy-efficient dynamic circuit design in the presence of crosstalk noise , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[26]  Pinaki Mazumder,et al.  Resonant tunneling diodes: models and properties , 1998, Proc. IEEE.

[27]  A. Alvandpour,et al.  A conditional keeper technique for sub-0.13/spl mu/ wide dynamic gates , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[28]  C.A.T. Salama,et al.  Charge redistribution and noise margins in domino CMOS logic , 1986 .

[29]  Pinaki Mazumder,et al.  Noise margins of threshold logic gates containing resonant tunneling diodes , 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).