Modeling of pocket implanted MOSFETs for anomalous analog behavior

Pocket implant is widely used in deep-sub-micron CMOS technologies to combat short channel effects. It, however, brings anomalously large drain-induced threshold voltage shift and low output resistance to long channel devices. This creates a serious problem for high-performance analog circuits. In this paper, the first physical model of these effects is proposed and verified against data from a 0.18 /spl mu/m technology. This model is suitable for SPICE modeling.

[1]  I. Chen,et al.  A 0.10 /spl mu/m gate length CMOS technology with 30 /spl Aring/ gate dielectric for 1.0 V-1.5 V applications , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[2]  C. Hu,et al.  Threshold voltage model for deep-submicrometer MOSFETs , 1993 .

[3]  H. Shichijo,et al.  Transistor design issues in integrating analog functions with high performance digital CMOS , 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).