An Architecture for Reconfigurable Multi-core Explorations

Multi-core systems are now the norm, and reconfigurable systems have shown substantial benefits over general purpose ones. This paper presents a combination of the two: a fully featured reconfigurable multi-core processor based on the Leon3 processor. The platform has important features like cache coherency, a fully running modern OS (GNU/Linux) and each core has a tightly coupled reconfigurable coprocessor unit attached. This allows the SPARC instruction set to be extended for the running application. The multi-core reconfigurable processor architecture, including the coprocessor interface, the ICAP controller and the Linux kernel driver, is presented. The experimental results show the characteristics of the platform including: area costs, the memory contention, the reprogramming cost... Speedups up to 100x are demonstrated on a cryptography test.

[1]  Michael D. Smith,et al.  A high-performance microarchitecture with hardware-programmable functional units , 1994, Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture.

[2]  Sergio López-Buedo,et al.  Implementation of secure applications in self-reconfigurable systems , 2008, Microprocess. Microsystems.

[3]  Gian Carlo Cardarilli,et al.  Algorithm acceleration on LEON-2 processor using a reconfigurable bit manipulation unit , 2010, 2010 8th Workshop on Intelligent Solutions in Embedded Systems.

[4]  Tianzhou Chen,et al.  A reconfigurable processor architecture combining multi-core and reconfigurable processing units , 2010, Telecommunication Systems.

[5]  Rudy Lauwereins,et al.  Reconfigurable instruction set processors: a survey , 2000, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668).

[6]  Yu-Kwong Kwok,et al.  On the design, control, and use of a reconfigurable heterogeneous multi-core system-on-a-chip , 2008, 2008 IEEE International Symposium on Parallel and Distributed Processing.

[7]  Ralph Wittig,et al.  OneChip: an FPGA processor with reconfigurable logic , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[8]  Barry J. Epstein,et al.  The Sparc Architecture Manual/Version 8 , 1992 .

[9]  Jeffrey J. Cook,et al.  Clustered programmable-reconfigurable processors , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

[10]  Jason Gait.  Validating the Correctness of Hardware Implementations of the NBS Data Encryption Standard , 1977 .

[11]  P. Amblard,et al.  Experiments Around Sparc Leon-2 For Mpeg Encoding , 2006, Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006..

[12]  Andreas Moshovos,et al.  CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).