The threshold voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula>) instability induced by gate stress has always been a significant reliability issue for silicon carbide (SiC) MOSFET. The negative bias temperature instability (NBTI) of 4H-SiC p-channel MOSFET (pMOS) was studied experimentally at 200 °C and compared with that of 4H-SiC n-channel MOSFET (nMOS). It is shown that the <inline-formula> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> drift of pMOS after 20 ks of negative stress −18 or −30 V is around twice that of nMOS. The behavior of the interface traps after stress is also analyzed quantitatively. It is concluded that the hole oxide traps are the dominant mechanism resulting in this large <inline-formula> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> drift difference between pMOS and nMOS, and the interface traps have little contribution to the threshold voltage drift in this study. Moreover, in a double logarithmic plot, the <inline-formula> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> recovery curves at a gate voltage of 0 V indicate that nMOS has a faster recovery than pMOS at the initial time. And the slope of <inline-formula> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> recovery curve for pMOS becomes larger after 100 s.