Generalized scaling theory and its application to a ¼ micrometer MOSFET design
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[1] C. Sah,et al. Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors☆ , 1966 .
[2] F. Stern,et al. Properties of Semiconductor Surface Inversion Layers in the Electric Quantum Limit , 1967 .
[3] F. Fang,et al. Transport Properties of Electrons in Inverted Silicon Surfaces , 1968 .
[4] F. Fang,et al. Hot Electron Effects and Saturation Velocities in Silicon Inversion Layers , 1970 .
[5] C. Mead,et al. Fundamental limitations in microelectronics—I. MOS technology , 1972 .
[6] R. Dennard,et al. Design of micron MOS switching devices , 1972 .
[7] K. Steinhubl. Design of Ion-Implanted MOSFET'S with Very Small Physical Dimensions , 1974 .
[8] R. M. Swanson,et al. Fundamental performance limits of MOS integrated circuits , 1975 .
[9] E. Bassous,et al. Improved Dielectric Reliability of SiO2 Films with Polycrystalline Silicon Electrodes , 1975 .
[10] Hayashi Yutaka. Static characteristics of extremely thin gate oxide m.o.s. transistors , 1975 .
[11] R.W. Keyes,et al. Physical limits in digital electronics , 1975, Proceedings of the IEEE.
[12] V. L. Rideout,et al. Very small MOSFET's for low-temperature operation , 1977, IEEE Transactions on Electron Devices.
[13] A. M. Mazzone,et al. Current transport in narrow-base transistors , 1977 .
[14] Tak H. Ning,et al. 1 pm MOSFET VLSI Technology: Part lV— Hot-Electron Design Constraints , 1979 .
[15] H. Sibbert,et al. Model and performance of hot-electron MOS transistors for VLSI , 1979, IEEE Transactions on Electron Devices.
[16] R.H. Dennard,et al. 1 µm MOSFET VLSI technology: Part II—Device designs and characteristics for high-performance logic applications , 1979, IEEE Transactions on Electron Devices.
[17] R.H. Dennard,et al. 1 µm MOSFET VLSI technology: Part IV—Hot-electron design constraints , 1979, IEEE Transactions on Electron Devices.
[18] R.H. Dennard,et al. 1 /spl mu/m MOSFET VLSI technology. II. Device designs and characteristics for high-performance logic applications , 1979, IEEE Journal of Solid-State Circuits.
[19] Hwa-Nien Yu,et al. 1 µm MOSFET VLSI technology: Part I—An overview , 1979, IEEE Transactions on Electron Devices.
[20] J. T. Clemens,et al. Characterization of the electron mobility in the inverted <100> Si surface , 1979, 1979 International Electron Devices Meeting.
[21] J. Meindl,et al. Performance limits of E/D NMOS VLSI , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[22] W. Fichtner,et al. Experimental and theoretical characterization of submicron MOSFETs , 1980, 1980 International Electron Devices Meeting.
[23] R. W. Coen,et al. Velocity of surface carriers in inversion layers on silicon , 1980 .
[24] Scaling the micron barrier with x-rays , 1980, 1980 International Electron Devices Meeting.
[25] P. Chatterjee,et al. The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI , 1980, IEEE Electron Device Letters.
[26] J. Plummer,et al. Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces , 1980 .
[27] M. Rudan,et al. Interpretation of C- V measurements for determining the doping profile in semiconductors , 1980 .
[28] D. F. Nelson,et al. Measurement of the high-field drift velocity of electrons in inversion layers on silicon , 1981, IEEE Electron Device Letters.
[29] Youssef A. El-Mansy. Limits to Scaling MOS Devices , 1981, 1981 Symposium on VLSI Technology. Digest of Technical Papers.
[30] R. H. Dennard. Technology challenges for ultrasmall silicon MOSFET's , 1981 .
[31] K.N. Ratnakumar,et al. New IGFET short-channel threshold voltage model , 1981, 1981 International Electron Devices Meeting.
[32] H. Shichijo,et al. A transmission line model for silicided diffusions: Impact on the performance of VLSI circuits , 1982, IEEE Transactions on Electron Devices.
[33] H. Shichijo. A re-examination of practical scalability limits of n-channel and p-channel MOS devices for VLSI , 1981, 1981 International Electron Devices Meeting.
[34] E. M. Buturla,et al. Finite-element analysis of semiconductor devices: the FIELDAY program , 1981 .
[35] D. Antoniadis,et al. Use of process and 2-D MOS simulation in the study of doping profile influence on S/D resistance in short channel MOSFET's , 1981, 1981 International Electron Devices Meeting.
[36] G. Baccarani,et al. Transconductance degradation in thin-Oxide MOSFET's , 1983, IEEE Transactions on Electron Devices.
[37] Y. Ohno. Short-channel MOSFET VT-VDScharacteristics model based on a point charge and its mirror images , 1982, IEEE Transactions on Electron Devices.
[38] B. L. Crowder,et al. Electrical Properties of Al/Ti Contact Metallurgy for VLSI Application , 1982 .
[39] A transmission line model for silicided diffusions: Impact on the performance of VLSI circuits , 1982, IEEE Transactions on Electron Devices.
[40] MOS Device and Technology Constraints in VLSI , 1982, IEEE Journal of Solid-State Circuits.
[41] Y. El-Mansy. MOS Device and technology constraints in VLSI , 1982, IEEE Transactions on Electron Devices.
[42] C. G. Sodini,et al. Charge accumulation and mobility in thin dielectric MOS transistors , 1982 .
[43] G. Baccarani,et al. Spreading resistance in submicron MOSFET's , 1983, IEEE Electron Device Letters.