Implementation issues in a multi-stage feed-forward analog neural network

Feed-forward multi-layer networks are used in conjunction with a variety of learning algorithms in a wide set of classification problems. Two of the major limitations on the size of hardware implementations are massive interconnectivity and the constraint of designing the whole network on a single substrate. An architecture is discussed that circumvents these problems and provides for simple interchip connections without sacrificing generality. Special attention is given to the practical problems of units and scales in the building blocks and the interfacing of successive modules when the system is decomposed into several sections, each on a separate chip.<<ETX>>