Dynamic voltage scaling with links for power optimization of interconnection networks

Originally developed to connect processors and memories in multicomputers, prior research and design of interconnection networks have focused largely on performance. As these networks get deployed in a wide range of new applications, where power is becoming a key design constraint, we need to seriously consider power efficiency in designing interconnection networks. As the demand for network bandwidth increases, communication links, already a significant consumer of power now, will take up an ever larger portion of total system power budget. In this paper we motivate the use of dynamic voltage scaling (DVS) for links, where the frequency and voltage of links are dynamically adjusted to minimize power consumption. We propose a history-based DVS policy that judiciously adjusts link frequencies and voltages based on past utilization. Our approach realizes up to 6.3/spl times/ power savings (4.6/spl times/ on average). This is accompanied by a moderate impact on performance (15.2% increase in average latency before network saturation and 2.5% reduction in throughput.) To the best of our knowledge, this is the first study that targets dynamic power optimization of interconnection networks.

[1]  D. Grunwald,et al.  The Performance of Multicomputer Interconnection Networks , 1987, Computer.

[2]  William J. Dally Virtual-channel flow control , 1990, ISCA '90.

[3]  Walter Willinger,et al.  On the self-similar nature of Ethernet traffic , 1993, SIGCOMM '93.

[4]  Robert W. Brodersen,et al.  High-efficiency low-voltage dc-dc conversion for portable applications , 1994 .

[5]  V. Paxson,et al.  Wide-area traffic: the failure of Poisson modeling , 1994, SIGCOMM.

[6]  Charles L. Seitz,et al.  Myrinet: A Gigabit-per-Second Local Area Network , 1995, IEEE Micro.

[7]  Sally Floyd,et al.  Wide area traffic: the failure of Poisson modeling , 1995, TNET.

[8]  Sudhakar Yalamanchili,et al.  Power constrained design of multiprocessor interconnection networks , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[9]  Walter Willinger,et al.  Self-similarity through high-variability: statistical analysis of Ethernet LAN traffic at the source level , 1997, TNET.

[10]  Soo-In Cho,et al.  A low-jitter mixed-mode DLL for high-speed DRAM applications , 2000, IEEE Journal of Solid-State Circuits.

[11]  W.J. Dally,et al.  Low-power area-efficient high-speed I/O circuit techniques , 2000, IEEE Journal of Solid-State Circuits.

[12]  William J. Dally,et al.  Flit-reservation flow control , 2000, Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550).

[13]  M. Horowitz,et al.  Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[14]  A variable-frequency parallel I/O interface with adaptive power supply regulation , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[15]  Thomas D. Burd,et al.  Design issues for Dynamic Voltage Scaling , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[16]  Niraj K. Jha,et al.  Low power system scheduling and synthesis , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[17]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[18]  William J. Bowhill,et al.  Design of High-Performance Microprocessor Circuits , 2001 .

[19]  Shubhendu S. Mukherjee,et al.  The Alpha 21364 network architecture , 2001, HOT 9 Interconnects. Symposium on High Performance Interconnects.

[20]  Jaeha Kim,et al.  Adaptive supply serial links with sub-1 V operation and per-pin clock recovery , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[21]  Henry Hoffmann,et al.  The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs , 2002, IEEE Micro.

[22]  R. Marculescu,et al.  Traffic analysis for on-chip networks design of multimedia applications , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[23]  Dragan Maksimovic,et al.  Closed-loop adaptive voltage scaling controller for standard-cell ASICs , 2002, ISLPED '02.

[24]  Sharad Malik,et al.  Orion: a power-performance simulator for interconnection networks , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..