Operating system support to an online hardware-software co-design scheduler for heterogeneous multicore architectures

This paper aims at designing and implementing a scheduler model for heterogeneous multiprocessor architectures based on software and hardware. As a proof of concept, the scheduler model was applied to the Linux operating system running on the SPARC Leon3 processor. In this sense, performance monitors have been implemented within the processors, which identify demands of processes in real-time. For each process, its demand is projected for the other processors in the architecture and then, it is performed a balancing to maximize the total system performance by distributing processes among processors. The Hungarian maximization algorithm, used in balancing scheduler was developed in hardware, and provides greater parallelism and performance in the execution of the algorithm. The scheduler has been validated through the parallel execution of several benchmarks, resulting in decreased execution times compared to the scheduler without the heterogeneity support.

[1]  Rami G. Melhem,et al.  Thread Assignment Optimization with Real-Time Performance and Memory Bandwidth Guarantees for Energy-Efficient Heterogeneous Multi-core Systems , 2012, 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium.

[2]  Stacey Jeffery,et al.  HASS: a scheduler for heterogeneous multicore systems , 2009, OPSR.

[3]  Norman P. Jouppi,et al.  Single-ISA heterogeneous multi-core architectures for multithreaded workload performance , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[4]  Stijn Eyerman,et al.  An efficient CPI stack counter architecture for superscalar processors , 2012, GLSVLSI '12.

[5]  James E. Smith,et al.  A Top-Down Approach to Architecting CPI Component Performance Counters , 2007, IEEE Micro.

[6]  Tong Li,et al.  Efficient operating system scheduling for performance-asymmetric multi-core architectures , 2007, Proceedings of the 2007 ACM/IEEE Conference on Supercomputing (SC '07).

[7]  Jaspal Singh.  Efficient Tasks scheduling for heterogeneous multiprocessor using Genetic algorithm with Node duplication , 2011 .

[8]  Sadagopan Srinivasan,et al.  Efficient interaction between OS and architecture in heterogeneous platforms , 2011, OPSR.

[9]  Hridesh Rajan,et al.  Predictive thread-to-core assignment on a heterogeneous multi-core processor , 2007, PLOS '07.

[10]  Hua Li,et al.  An FPGA-based acceleration platform for auction algorithm , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[11]  Lieven Eeckhout,et al.  Scheduling heterogeneous multi-cores through performance impact estimation (PIE) , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).

[12]  Manuel Prieto,et al.  Leveraging Core Specialization via OS Scheduling to Improve Performance on Asymmetric Multicore Systems , 2012, TOCS.

[13]  Patrick Crowley,et al.  Dynamic thread assignment on heterogeneous multiprocessor architectures , 2006, CF '06.

[14]  Vishakha Gupta,et al.  Kinship: efficient resource management for performance and functionally asymmetric platforms , 2013, CF '13.

[15]  Harold W. Kuhn,et al.  The Hungarian method for the assignment problem , 1955, 50 Years of Integer Programming.

[16]  Dheeraj Reddy,et al.  Bias scheduling in heterogeneous multi-core architectures , 2010, EuroSys '10.

[17]  Dimitri P. Bertsekas,et al.  Auction algorithms for network flow problems: A tutorial introduction , 1992, Comput. Optim. Appl..

[18]  Jason Cong,et al.  Energy-efficient scheduling on heterogeneous multi-core architectures , 2012, ISLPED '12.