Incremental synthesis

A small change in the input to logic synthesis may cause a large change in the output implementation. This is undesirable if a designer has some investment in the old implementation and does not want it perturbed more than necessary. We describe a method that solves this problem by reusing gates from the old implementation, and restricting synthesis to the modified portions only.

[1]  Ibrahim N. Hajj,et al.  ACCORD : Automatic Catching and Correction of Logic Design Errors in Combinational Circuits , 1992, Proceedings International Test Conference 1992.

[2]  Robert K. Brayton,et al.  Incremental synthesis for engineering changes , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[3]  Koichiro Ishihara,et al.  Incremental Logic Synthesis through Gate Logic Structure Identification , 1986, 23rd ACM/IEEE Design Automation Conference.

[4]  Irith Pomeranz,et al.  On diagnosis and correction of design errors , 1993, ICCAD.

[5]  Daniel Brand Verification of large synthesized designs , 1993, ICCAD.

[6]  Masahiro Fujita,et al.  Application of Boolean unification to combinational logic synthesis , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[7]  Olivier Coudert,et al.  Automating the diagnosis and the rectification of design errors with PRIAM , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.