Package and chip design optimization for mid-frequency power distribution decoupling

In this paper the mid-frequency power supply noise has been studied for a complex, next generation computer system by simulations of the complete module and board power distribution system. An MCM-D and MCM-C design and the effectiveness of on-chip and discrete on-module decoupling capacitors have been compared. The impact of delta-I ramping over several cycles and the impact of the continuous background switching and on-chip leakage have been analyzed. Conclusions are presented to optimize the chip and package design.

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