Simultaneous scheduling, binding and layer assignment for synthesis of vertically integrated 3D systems

Three-dimensional vertically integrated systems allow active devices to be placed on multiple device layers. In recent years, a number of research efforts have addressed physical synthesis issues for such systems. Such efforts showed a significant reduction in interconnect lengths. In order to effectively synthesize designs for 3D systems, it is necessary to take layer assignment for resources into consideration at higher levels of the design abstraction. We address the layer assignment problem as a part of a physical aware behavioral synthesis flow. We propose a 0-1 linear program formulation to perform simultaneous and optimal scheduling, binding and layer assignment for synthesizing designs for three-dimensional vertically integrated systems. The objective is to minimize inter-stratal via and the interconnect length in the critical path while taking thermal gradient between layers into account (which has been shown to be of particular concern for 3D systems). Floorplanning is performed for the synthesized design in order to estimate interconnect lengths. Results show a reduction of approximately 37% in total interconnect lengths on an average, compared to a traditional two-dimensional implementation when 2-5 layer implementations are examined.

[1]  Anantha Chandrakasan,et al.  Calibration of Rent's rule models for three-dimensional integrated circuits , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Pierre Hansen,et al.  State-of-the-Art Survey - Constrained Nonlinear 0-1 Programming , 1993, INFORMS J. Comput..

[3]  Kaustav Banerjee,et al.  Interconnect limits on gigascale integration (GSI) in the 21st century , 2001, Proc. IEEE.

[4]  Yeong-Dae Kim,et al.  A linear programming-based algorithm for floorplanning in VLSI design , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Ranga Vemuri,et al.  Specification of Control Flow Properties for Verification of Synthesized VHDL Designs , 1996, FMCAD.

[6]  Pierre Hansen,et al.  Constrained Nonlinear 0-1 Programming , 1989 .

[7]  Catherine H. Gebotys Optimal synthesis of multichip architectures , 1992, ICCAD.

[8]  Jae-Hoon Kim,et al.  Layout-driven resource sharing in high-level synthesis , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

[9]  R. Reif,et al.  Thermal analysis of three-dimensional (3-D) integrated circuits (ICs) , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

[10]  Wayne Luk,et al.  Heuristic datapath allocation for multiple wordlength systems , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[11]  Kaustav Banerjee,et al.  3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.

[12]  Anantha Chandrakasan,et al.  Three-dimensional integrated circuits: performance, design methodology, and CAD tools , 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

[13]  Wayne H. Wolf,et al.  TGFF: task graphs for free , 1998, Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98).

[14]  Yangdong Deng,et al.  Interconnect characteristics of 2.5-D system integration scheme , 2001, ISPD '01.

[15]  Anna W. Topol,et al.  Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication , 2002, Digest. International Electron Devices Meeting,.

[16]  James D. Meindl,et al.  Interconnect limits on gigascale integration (GSI) , 2001, 2001 6th International Symposium on Plasma- and Process-Induced Damage (IEEE Cat. No.01TH8538).

[17]  James A. Hutchby,et al.  Limits to binary logic switch scaling - a gedanken model , 2003, Proc. IEEE.

[18]  Payman Zarkesh-Ha,et al.  Impact of three-dimensional architectures on interconnects in gigascale integration , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[19]  Majid Sarrafzadeh,et al.  Integrating scheduling and physical design into a coherent compilation cycle for reconfigurable computing architectures , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[20]  J. Joyner,et al.  Opportunities for reduced power dissipation using three-dimensional integration , 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).

[21]  Rajesh K. Gupta,et al.  A case analysis of system partitioning and its relationship to high-level synthesis tasks , 1998, Proceedings Eleventh International Conference on VLSI Design.