Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations

A run-time reconfiguable array of multipliers architecture is introduced. The novel multiplier can be easily reconfigured to trade bitwidth for array size, thus maximizing the utilization of available hardware, multiply signed or unsigned data, and uses part of its structure when needed. The proposed reconfigurable circuit consists of an array of m×m multipliers, a few arrays of adders each adding three numbers, and switches. Also small blocks for the implementation of the reconfiguration capabilities, mentioned above, consist of adders, multiplexers, inverters, coders and registers. The circuit reconfiguration can be done dynamically through using only a few control bits. The architecture design of the reconfigurable multiplier, with hardware equivalent to one 64×64 bit high precision multiplier, which can be dynamically reconfigured to produce an array of the products in different forms is described in detailed manner.