Scalable Run Time Reconfigurable Architecture

Currently multi-FPGA reconfigurable computing systems are still commonly used for accelerating algorithms. This technology where acceleration is achieved by spatial implementation of an algorithm in reconfigurable hardware has proven to be feasible. However, the best suiting algorithms are those who are very structured, can benefit from deep pipelining and need only local communication resources. Many algorithms can not fulfil the third requirement once the problem size grows and multi-FPGA systems become necessary. In this paper we address the emulation of a run time reconfigurable processor architecture, which scales better for this kind of computing problems.