Design of a low-cost VLSI architecture for 1.6 kbps speech synthesis

We present a low-cost architecture for speech synthesis at 1.6 kbps. The speech synthesis algorithm is formulated in terms of a hardware-oriented design. Based on our proposed speech vocoder, the novel architecture consumes lower hardware resources and is therefore suited for hardware implementation.

[1]  Lawrence R. Rabiner,et al.  A pattern recognition approach to voiced-unvoiced-silence classification with applications to speech recognition , 1976 .

[2]  Robert M. Gray,et al.  An Algorithm for Vector Quantizer Design , 1980, IEEE Trans. Commun..

[3]  Jhing-Fa Wang,et al.  Single chip implementation of the 1.6 kbps speech vocoder , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[4]  Xingjun Wu,et al.  LSP speech synthesis ASIC architecture , 1995, Proceedings of 4th International Conference on Solid-State and IC Technology.

[5]  D G Childers,et al.  Speech synthesis by glottal excited linear prediction. , 1994, The Journal of the Acoustical Society of America.

[6]  J. Makhoul,et al.  Linear prediction: A tutorial review , 1975, Proceedings of the IEEE.