High-level synthesized 2-D IDCT/IDST implementation for HEVC codecs on FPGA

This paper presents efficient inverse discrete cosine transform (IDCT) and inverse discrete sine transform (IDST) implementations for High Efficiency Video Coding (HEVC). The proposal makes use of high-level synthesis (HLS) to implement a complete HEVC 2-D IDCT/IDST architecture directly from the C code of a well-known Even-Odd decomposition algorithm. The final architecture includes a 4-point IDCT/IDST unit for the smallest transform blocks (TB), an 8/16/32-point IDCT unit for the other TBs, and a transpose memory for intermediate results. On Arria II FPGA, it supports real-time (60 fps) HEVC decoding of up to 2160p format with 12.4 kALUTs and 344 DSP blocks. Compared with the other existing HLS approach, the proposed solution is almost 5 times faster and is able to utilize available FPGA resources better.

[1]  Madhukar Budagavi,et al.  Core Transform Design in the High Efficiency Video Coding (HEVC) Standard , 2013, IEEE Journal of Selected Topics in Signal Processing.

[2]  Grzegorz Pastuszak,et al.  Algorithm and Architecture Design of the H.265/HEVC Intra Encoder , 2016, IEEE Transactions on Circuits and Systems for Video Technology.

[3]  Timo Hämäläinen,et al.  High-level synthesis implementation of HEVC 2-D DCT/DST on FPGA , 2017, 2017 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

[4]  Antti Hallapuro,et al.  Comparative Rate-Distortion-Complexity Analysis of HEVC and AVC Video Codecs , 2012, IEEE Transactions on Circuits and Systems for Video Technology.

[5]  Daniel Gajski,et al.  Introduction to high-level synthesis , 1994, IEEE Design & Test of Computers.

[6]  Bruno Zatt,et al.  Power efficient and high troughtput multi-size IDCT targeting UHD HEVC decoders , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

[7]  Ilker Hamzaoglu,et al.  A low energy HEVC inverse transform hardware , 2014, IEEE Transactions on Consumer Electronics.

[8]  Ilker Hamzaoglu,et al.  FPGA implementations of HEVC Inverse DCT using high-level synthesis , 2015, 2015 Conference on Design and Architectures for Signal and Image Processing (DASIP).