Towards Dynamically Reconfigurable SoCs (DRSoCs) in industrial automation: State of the art, challenges and opportunities

Abstract In this paper we analyze the state of the IEC 61499 standard for the specification of distributed control systems (DCS). First, we discuss the limitations of previous efforts regarding the implementation of DCS, as well as the rationale for the introduction of the IEC 61499. Then, we embark in a succinct analysis of the standard and the associated models for DCS platforms, outlining the main barriers that have hindered its widespread adoption. We argue that a common architectural framework (which is currently lacking) for implementing full-fledged IEC 61499 is necessary, especially if features such as fine-grained distribution and reconfiguration are to be supported. We posit that Dynamically Reconfigurable Systems on Chip (DRSoCs) represent an excellent implementation choice for enabling such platforms,thanks to the strides made by the reconfigurable computing community in recent years, in terms of tools for implementing such systems, but also in new architectural principles and design paradigms based on Reconfigurable OSes. Moreover, we provide some compelling reasons for bringing those two domains together, as well as the challenges that need to be overcome in order to harmonize both efforts.

[1]  Jean-Philippe Diguet,et al.  A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-Chip , 2018, J. Parallel Distributed Comput..

[2]  Bartosz Trybus,et al.  Architecture of FPGA Embedded Multiprocessor Programmable Controller , 2015, IEEE Transactions on Industrial Electronics.

[3]  Thomas I. Strasser,et al.  Design and Execution Issues in IEC 61499 Distributed Automation and Control Systems , 2011, IEEE Transactions on Systems, Man, and Cybernetics, Part C (Applications and Reviews).

[4]  Francky Catthoor,et al.  Efficiently scheduling runtime reconfigurations , 2008, TODE.

[5]  Ulrich Rückert,et al.  REPLICA: a bitstream manipulation filter for module relocation in partial reconfigurable systems , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[6]  Thomas I. Strasser,et al.  Developing modular reusable IEC 61499 control applications with 4DIAC , 2013, 2013 11th IEEE International Conference on Industrial Informatics (INDIN).

[7]  Kazuo Yamazaki,et al.  A study on the generation of silicon-based hardware Plc by means of the direct conversion of the ladder diagram to circuit design language , 2010 .

[8]  Samy Meftali,et al.  Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: A Xilinx EDK case study , 2012, 2012 International Conference on Reconfigurable Computing and FPGAs.

[9]  Valeriy Vyatkin,et al.  OOONEIDA: an open, object-oriented knowledge economy for intelligent distributed automation , 2003, IEEE International Conference on Industrial Informatics, 2003. INDIN 2003. Proceedings..

[10]  Raphael Rubin,et al.  Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP) , 2016, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

[11]  Hiroshi Yamamoto,et al.  An FPGA implementation of hard‐wired sequence control system based on PLC software , 2011 .

[12]  C. Veber,et al.  Implementation approaches for the execution model of IEC 61499 applications , 2004, 2nd IEEE International Conference on Industrial Informatics, 2004. INDIN '04. 2004.

[13]  Valeriy Vyatkin,et al.  Redesign Distributed PLC Control Systems Using IEC 61499 Function Blocks , 2012, IEEE Transactions on Automation Science and Engineering.

[14]  Eduardo de la Torre,et al.  Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems , 2012, 2012 International Conference on Reconfigurable Computing and FPGAs.

[15]  Valeriy Vyatkin,et al.  Software Engineering in Industrial Automation: State-of-the-Art Review , 2013, IEEE Transactions on Industrial Informatics.

[16]  L Idkhajine,et al.  FPGA-based Controllers , 2011, IEEE Industrial Electronics Magazine.

[17]  Johnny Öberg,et al.  The RecoBlock SoC platform: A flexible array of reusable Run-Time-Reconfigurable IP-blocks , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[18]  Pao-Ann Hsiung,et al.  Hardware Task Scheduling and Placement in Operating Systems for Dynamically Reconfigurable SoC , 2005, EUC.

[19]  Reiner W. Hartenstein,et al.  Basics of Reconfigurable Computing , 2007 .

[20]  Abderrezak Guessoum,et al.  A novel methodology for accelerating bitstream relocation in partially reconfigurable systems , 2013, Microprocess. Microsystems.

[21]  Brent E. Nelson,et al.  Tincr — A custom CAD tool framework for Vivado , 2014, 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14).

[22]  Daniel Gajski,et al.  Introduction to high-level synthesis , 1994, IEEE Design & Test of Computers.

[23]  Jon Perez,et al.  R3TOS: A Novel Reliable Reconfigurable Real-Time Operating System for Highly Adaptive, Efficient, and Dependable Computing on FPGAs , 2013, IEEE Transactions on Computers.

[24]  Juanjo Noguera,et al.  Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling , 2004, TECS.

[25]  Christian Haubelt,et al.  Electronic System-Level Synthesis Methodologies , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[26]  Jonathan Rose,et al.  Quantifying and Exploring the Gap Between FPGAs and ASICs , 2009 .

[27]  Henk Corporaal,et al.  An automated technique to generate relocatable partial bitstreams for Xilinx FPGAs , 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

[28]  Marco Platzner,et al.  ReconOS: Multithreaded programming for reconfigurable computers , 2009, TECS.

[29]  C. Sunder,et al.  Considering IEC 61131-3 and IEC 61499 in the context of component frameworks , 2008, 2008 6th IEEE International Conference on Industrial Informatics.

[30]  Brent E. Nelson,et al.  RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

[31]  Dhanashri Gawali,et al.  FPGA Based Micro-PLC Design Approach , 2009, 2009 International Conference on Advances in Computing, Control, and Telecommunication Technologies.

[32]  Jürgen Teich,et al.  ReCoBus-Builder — A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[33]  Adam Milik,et al.  On hardware synthesis and implementation of PLC programs in FPGAs , 2016, Microprocess. Microsystems.

[34]  Jean-Didier Legat,et al.  An Evaluation of Dynamic Partial Reconfiguration for Signal and Image Processing in Professional Electronics Applications , 2008, EURASIP J. Embed. Syst..

[35]  Valeriy Vyatkin,et al.  On Definition of a Formal Model for IEC 61499 Function Blocks , 2008, EURASIP J. Embed. Syst..

[36]  Steven J. E. Wilton,et al.  Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices , 2013, 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines.

[37]  V. Vyatkin.  The IEC 61499 standard and its semantics , 2009, IEEE Industrial Electronics Magazine.

[38]  Valeriy Vyatkin,et al.  On composition of mechatronic components enabled by interoperability and portability provisions of IEC 61499: A case study , 2013, 2013 IEEE 18th Conference on Emerging Technologies & Factory Automation (ETFA).

[39]  Gordon J. Brebner,et al.  The swappable logic unit: a paradigm for virtual hardware , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[40]  Alois Zoitl,et al.  Real-Time Execution for IEC 61499 , 2008 .

[41]  Barry E. Mullins,et al.  Using Relocatable Bitstreams for Fault Tolerance , 2012, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).

[42]  Kleanthis Thramboulidis,et al.  Challenges in the development of Mechatronic systems: The Mechatronic Component , 2008, 2008 IEEE International Conference on Emerging Technologies and Factory Automation.

[43]  Mark D. Hill,et al.  Amdahl's Law in the Multicore Era , 2008 .

[44]  Francisco Moya,et al.  Persistence Management Model for Dynamically Reconfigurable Hardware , 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

[45]  Serge Weber,et al.  A Novel Framework for the Design of Adaptable Reconfigurable Partitions for the Placement of Variable-sized IP Cores , 2014, IEEE Embedded Systems Letters.

[46]  Jean-Luc Dekeyser,et al.  Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems , 2012, 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC).

[47]  Michael J. Schulte,et al.  An Overview of Reconfigurable Hardware in Embedded Systems , 2006, EURASIP J. Embed. Syst..

[48]  Philippe Coussy,et al.  High-Level Synthesis: from Algorithm to Digital Circuit , 2008 .

[49]  J. Palicot,et al.  Partial Reconfiguration of FPGAs for Dynamical Reconfiguration of a Software Radio Platform , 2007, 2007 16th IST Mobile and Wireless Communications Summit.

[50]  Phillip H. Jones,et al.  Hotspot Mitigation Using Dynamic Partial Reconfiguration for Improved Performance , 2009, 2009 International Conference on Reconfigurable Computing and FPGAs.

[51]  Éric Rutten,et al.  Extending UML/MARTE to Support Discrete Controller Synthesis, Application to Reconfigurable Systems-on-Chip Modeling , 2014, TRETS.

[52]  Kleanthis Thramboulidis,et al.  A Real-Time-Linux-Based Framework for Model-Driven Engineering in Control and Automation , 2011, IEEE Transactions on Industrial Electronics.

[53]  Donal Heffernan,et al.  VHDL architecture for IEC 61499 function blocks , 2010, IET Comput. Digit. Tech..

[54]  Roberto Passerone,et al.  A Platform-Based Taxonomy for ESL Design , 2006, IEEE Design & Test of Computers.

[55]  Sen Wang,et al.  VTR 7.0: Next Generation Architecture and CAD System for FPGAs , 2014, TRETS.

[56]  Eric Monmasson,et al.  Industrial electronic control: FPGAs and embedded systems solutions , 2013, IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society.

[57]  Loïc Lagadec,et al.  A design approach to automatically generate on-chip monitors during high-level synthesis of hardware accelerator , 2014, GLSVLSI '14.

[58]  Valeriy Vyatkin,et al.  Essential elements for programming of distributed automation and control systems , 2013, 2013 IEEE 18th Conference on Emerging Technologies & Factory Automation (ETFA).

[59]  Jürgen Becker,et al.  RAMPSoCVM: Runtime Support and Hardware Virtualization for a Runtime Adaptive MPSoC , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

[60]  Heiko Kalte,et al.  Context saving and restoring for multitasking in reconfigurable systems , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[61]  Roger Woods,et al.  FPGA-based Implementation of Signal Processing Systems , 2017 .

[62]  Kleanthis Thramboulidis.  IEC 61499: Back to the well proven practice of IEC 61131? , 2012, Proceedings of 2012 IEEE 17th International Conference on Emerging Technologies & Factory Automation (ETFA 2012).

[63]  Edward Hrynkiewicz,et al.  A FPGA-based bit-word PLC CPUs development platform , 2010, PDeS.

[64]  Jean-Philippe Diguet,et al.  Kaolin: A system-level AADL tool for FPGA design reuse, upgrade and migration , 2015, 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[65]  Douglas L. Maskell,et al.  Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform , 2014, J. Signal Process. Syst..

[66]  Diana Göhringer,et al.  RePaBit: Automated generation of relocatable partial bitstreams for Xilinx Zynq FPGAs , 2016, 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

[67]  Jürgen Teich,et al.  Partial reconfiguration on FPGAs in practice — Tools and applications , 2012, ARCS 2012.

[68]  Alberto L. Sangiovanni-Vincentelli,et al.  Quo Vadis, SLD? Reasoning About the Trends and Challenges of System Level Design , 2007, Proceedings of the IEEE.

[69]  Scott Hauck,et al.  Performance of partial reconfiguration in FPGA systems: A survey and a cost model , 2011, TRETS.

[70]  Éric Rutten,et al.  An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems , 2015, ACM Trans. Design Autom. Electr. Syst..

[71]  Jürgen Jasperneite,et al.  An architectural approach for reconfigurable industrial I/O devices , 2014, 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14).

[72]  Rudy Lauwereins,et al.  Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[73]  A. Zoitl,et al.  A reconfigurable communication gateway for distributed embedded control systems , 2012, IECON 2012 - 38th Annual Conference on IEEE Industrial Electronics Society.

[74]  Christian Gerber,et al.  From IEC 61131 to IEC 61499 for Distributed Systems: A Case Study , 2008, EURASIP J. Embed. Syst..

[75]  A. Zoitl,et al.  Is IEC 61499 in harmony with IEC 61131-3? , 2009, IEEE Industrial Electronics Magazine.

[76]  Jim Tørresen,et al.  Design Tools for Implementing Self-Aware and Fault-Tolerant Systems on FPGAs , 2014, TRETS.

[77]  Peter M. Athanas,et al.  OpenPR: An Open-Source Partial-Reconfiguration Toolkit for Xilinx FPGAs , 2011, 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum.