MMW lab In-Situ to extract noise parameters of 65nm CMOS aiming 70∼90GHz applications

In this paper, the design and use of an In-Situ Tuner (IST) aiming On-Wafer multi-impedance method are presented. The conventional method using Off-Wafer Tuner is limited by the frequency range and has losses between this external Tuner and the Device Under Test (DUT). Here, IST is placed near the DUT to achieve higher |Γ| and to cancel losses between the impedance generator and the device. The architecture of the Tuner is based on variable lumped R and C elements fulfilled with Cold-FET and varactors controlled through biasing and associated to coplanar transmission line (cpw-TL) for phase shifting. Detailed and dedicated noise de-embedding technique is described to extract the 4 noise (NFmin, Rn, Γopt) parameters of a 65nm MOSFETs silicon transistor through the use of this in-situ multi-impedance method. The 75–110GHz noise test bench using cold-noise source method and the noise measurement are described showing Transistor capabilities at MMW.