An asymmetric channel SOI nMOSFET for improving DC and microwave characteristics
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[1] J. Raskin,et al. Determining the reference impedance of on-wafer TLR calibrations on tossy substrates , 1996, 1996 26th European Microwave Conference.
[2] M. Y. Hong. Simulation and fabrication of submicron channel length DMOS transistors for analog applications , 1993 .
[3] S. M. Sze,et al. Physics of semiconductor devices , 1969 .
[4] J. Raskin,et al. Accurate SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modeling , 1998 .
[5] O. Faynot,et al. Fully-depleted 0.25 /spl mu/m SOI devices for low power RF mixed analog-digital circuits , 1998, 1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199).
[6] S. Odanaka,et al. Potential design and transport property of 0.1-/spl mu/m MOSFET with asymmetric channel profile , 1997 .
[7] J.-P. Raskin,et al. Microwave Integrated CMOS Oscillators on Silicon-on-Insulator Substrate , 2000, 2000 30th European Microwave Conference.
[8] R. Logan,et al. RF potential of a 0.18-/spl mu/m CMOS logic technology , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).
[9] M. Hargrove,et al. RF potential of a 0.18-/spl mu/m CMOS logic device technology , 2000 .
[10] Denis Flandre,et al. An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics , 1999 .