Design of cache memories for dataflow architecture

Abstract The recent advance in dataflow processing — to combine the dataflow paradigm with the control-flow paradigm — has brought out many new challenging issues. This hybrid organization has made it possible to study and adapt familiar control-flow concepts such as cache memories within the framework of the dataflow architecture. The concept of cache memory has proven its effectiveness in the von Neumann architecture due to the spatial and temporal localities which govern the organization of the conventional programming execution. A dataflow paradigm, does not informally support locality, since the execution sequence is enforced only by the availability of operands. However, dataflow programs can be reordered based on various criteria to enhance the locality of instruction references. This can be achieved by: (i) careful partitioning of a dataflow program into vertical layers of data dependent instructions; and (ii) proper distribution and allocation of the recurrence portions of the dataflow program. Enhancing the locality of data references in the dataflow architecture is a more challenging problem. This paper studies the design of instruction, data (operand), and I-Structure cache memories using the Explicit Token Store (ETS) model of dataflow system. The performance results obtained using various benchmark programs are presented and analyzed.

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