Virtual Architectures for partial runtime reconfigurable systems. Application to Network on Chip based SoC emulation

The paper presents a method for designing Virtual Architectures (VAs) for partial runtime reconfigurable systems (pRTRs). The presented method permits to create flexible pRTRs. Such pRTR system is used as a core for a Network on Chip based SoC emulation. The main advantage of the emulation framework is that it permits fast emulation and design space exploration. The paper includes a brief description of all the building elements of the emulation framework and a use case that demonstrates the advantages of the designed pRTRs.

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