论文信息 - Design and Implementation of a Low Power Ternary Full Adder

Design and Implementation of a Low Power Ternary Full Adder

The ternary full adder has been fabricated in MOSIS two micron n-well CMOS technology. The full adder and its building blocks, NTI and PTI have been tested experimentally for static and dynamic performance, compared with the SPICE simulated behavior, and close agreement is observed. The ternary-valued logic circuits designed in the present work which do not use depletion mode MOSFETS perform better than that implemented earlier inDECMOS technology. The present design is fully compatible with the currentCMOS technology, uses fewer components and dissipates power in the microwatt range.

A. Srivastava | K. Venkatapathy | A. Srivastava | K. Venkatapathy

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