Split gate flash memory cells using source side enhanced hot electron injection are commonly used in stand-alone memories and embedded systems. Scaling the split gate cell poses major difficulties associated with engineering of the "gap region" between the floating gate and select gate. During thermal oxidation to grow the interpoly oxide, the 2-dimensional nature of oxide growth produces a sharp reentrant corner between the select gate and the floating gate, and also forms a bird's beak under the floating gate. We show that these mechanisms can degrade both the reliability and performance of the split gate device. In this paper, we present the analysis, integration, and complete characterization of a high performance, robust split-gate memory cell using a composite dielectric. The data clearly shows a 3/spl times/ improvement in performance and superior reliability over conventional fabrication techniques.