An efficient 3D NoC synthesis by using genetic algorithms

The application of 3D Network on Chip (NoC) provides an effective way for tackling the performance bottleneck for high-performance Systems on Chips (SoCs). How to design an efficient 3D Network on Chip which is satisfied with the communication requirement of 3D system and simultaneously enables significant performance enhancements has encouraged a lot of attention. In this paper, we focus on the automatic design for custom based NoC architecture by use of a novel approach. The synthesis idea is proposed to develop a minimum cost topology and an optimized floorplan to decrease the power consumption, under the hardware and software constraints. Different algorithms are used to solve the sub-problems. In the core to switch connectivity stage, we firstly use Tarjan Algorithm to find the strong connectivity part in the core communication graph, and then use the Min-cut Algorithm to partition the core communication graph into sub-graphs. To establish the switch to switch connection, we apply Genetic Algorithm (GA) to do the path computation and flow control. Finally, we use Genetic Algorithm to solve the switch position problem. Optimized positions of switches in the floorplan for minimizing the power consumption are obtained while meeting the non-overlapping constraints. The experimental results show that our proposed synthesis approach is efficient and much power saving in the application of NoC design work.

[1]  Luca Benini,et al.  Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow , 2007, Nano-Net.

[2]  Kees G. W. Goossens,et al.  A unified approach to constrained mapping and routing on network-on-chip architectures , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[3]  Robert E. Tarjan,et al.  Depth-First Search and Linear Graph Algorithms , 1972, SIAM J. Comput..

[4]  Jason Cong,et al.  A thermal-driven floorplanning algorithm for 3D ICs , 2004, ICCAD 2004.

[5]  Eby G. Friedman,et al.  3-D Topologies for Networks-on-Chip , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Srinivasan Murali,et al.  SUNMAP: a tool for automatic topology selection and generation for NoCs , 2004, Proceedings. 41st Design Automation Conference, 2004..

[7]  Jason Cong,et al.  Thermal-driven multilevel routing for 3-D ICs , 2005, Asia and South Pacific Design Automation Conference.

[8]  Luca Benini,et al.  Designing Application-Specific Networks on Chips with Floorplan Information , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[9]  Li Shang,et al.  3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[10]  Luca Benini,et al.  Networks on chips - technology and tools , 2006, The Morgan Kaufmann series in systems on silicon.

[11]  Mechthild Stoer,et al.  A simple min-cut algorithm , 1997, JACM.

[12]  Alberto L. Sangiovanni-Vincentelli,et al.  Efficient synthesis of networks on chip , 2003, Proceedings 21st International Conference on Computer Design.

[13]  Sung Kyu Lim,et al.  Physical design for 3D system on package , 2005, IEEE Design & Test of Computers.

[14]  Mitsuo Gen,et al.  Network Models and Optimization: Multiobjective Genetic Algorithm Approach , 2008 .

[15]  R. Marculescu,et al.  Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[16]  Narayanan Vijaykrishnan,et al.  Interconnect and thermal-aware floorplanning for 3D microprocessors , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[17]  Emanuel Falkenauer,et al.  Genetic Algorithms and Grouping Problems , 1998 .

[18]  Sri Parameswaran,et al.  NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks , 2008, 2008 Asia and South Pacific Design Automation Conference.

[19]  Srinivasan Murali,et al.  Bandwidth-constrained mapping of cores onto NoC architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[20]  Luca Benini,et al.  Synthesis of networks on chips for 3D systems on chips , 2009, 2009 Asia and South Pacific Design Automation Conference.

[21]  Luca Benini,et al.  NoC synthesis flow for customized domain specific multiprocessor systems-on-chip , 2005, IEEE Transactions on Parallel and Distributed Systems.