Testing high resolution SD ADC’s by using the noise transfer function

A new solution to improve the testability of high resolution SD Analogue to Digital Converters (SD ADC’s) using the quantizer input as test node is described. The theoretical basis for the technique is discussed and results from high level simulations for a 16 bit, 4th order, audio ADC are presented. The analysis demonstrates the potential to reduce the computational effort associated with test response analysis versus conventional techniques.

[1]  James C. Candy,et al.  A Use of Double Integration in Sigma Delta Modulation , 1985, IEEE Trans. Commun..

[2]  Thomas Almy,et al.  HABIST: histogram-based analog built in self test , 1997, Proceedings International Test Conference 1997.

[3]  Gordon W. Roberts,et al.  A BIST scheme for an SNR test of a sigma-delta ADC , 1993, Proceedings of IEEE International Test Conference - (ITC).

[4]  Florence Azaïs,et al.  Implementation of a linear histogram BIST for ADCs , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[5]  Stephen K. Sunter,et al.  A simplified polynomial-fitting algorithm for DAC and ADC BIST , 1997, Proceedings International Test Conference 1997.

[6]  Abhijit Chatterjee,et al.  A signature analyzer for analog and mixed-signal circuits , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[7]  Narumi Sakashita,et al.  A built-in self-test for ADC and DAC in a single-chip speech CODEC , 1993, Proceedings of IEEE International Test Conference - (ITC).

[8]  Aubin Roy,et al.  High accuracy stimulus generation for A/D converter BIST , 2002, Proceedings. International Test Conference.