Taylor expansion diagrams: a new representation for RTL verification

A new, compact, canonical representation for arithmetic expressions, called Taylor expansion diagram, is presented. This representation is based on a non-binary decomposition principle. It treats the expression as a continuous, differentiable function and applies Taylor series expansion recursively over its symbolic variables. The resulting Taylor expansion diagram (TED) is canonical for a fixed variable order. We present a theory of TED, and show how to obtain a reduced, normalized representation. We demonstrate that it has linear space complexity for arbitrarily complex polynomials, while time complexity to generate the representation is comparable to that of *BMD. The proposed TED representation is intended to facilitate the verification of RTL specifications and hard. ware implementations of arithmetic designs, and especially the equivalence checking of complex arithmetic expressions that arise in symbolic verification.

[1]  Shuzo Yajima,et al.  Manipulation of Large-Scale Polynomials Using BMDs : Special Section on VLSI Design and CAD Algorithms , 1997 .

[2]  Herbert B. Enderton,et al.  A mathematical introduction to logic , 1972 .

[3]  Zheng Zhou,et al.  Equivalence Checking of Datapaths Based on Canonical Arithmetic Expressions , 1995, 32nd Design Automation Conference.

[4]  Kenneth L. McMillan,et al.  Symbolic model checking , 1992 .

[5]  Wolfgang Rosenstiel,et al.  Multilevel logic synthesis based on functional decision diagrams , 1992, [1992] Proceedings The European Conference on Design Automation.

[6]  Tiziano Villa,et al.  VIS: A System for Verification and Synthesis , 1996, CAV.

[7]  Richard Gerber,et al.  Verifying systems with integer constraints and Boolean predicates: a composite approach , 1998, ISSTA '98.

[8]  E.M. Clarke,et al.  Hybrid decision diagrams. Overcoming the limitations of MTBDDs and BMDs , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[9]  S. Minato.  Implicit manipulation of polynomials using zero-suppressed BDDs , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[10]  Masahiro Fujita,et al.  Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping , 1997, Formal Methods Syst. Des..

[11]  Rolf Drechsler,et al.  Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams , 1994, 31st Design Automation Conference.

[12]  R. I. Bahar,et al.  Algebraic decision diagrams and their applications , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[13]  David L. Dill,et al.  A decision procedure for bit-vector arithmetic , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[14]  Kurt Keutzer,et al.  Design verification and reachability analysis using algebraic manipulation , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[15]  R. Drechsler,et al.  Formal verification of word-level specifications , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[16]  Rolf Drechsler,et al.  The K*BMD: A Verification Data Structure , 1997, IEEE Des. Test Comput..

[17]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[18]  R. Bryant,et al.  Verification of Arithmetic Functions with Binary Moment Diagrams , 1994 .