Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers

In this paper, the tapered-VTH methodology to design energy-efficient buffers in deep nanometer CMOS technology is deeply analyzed. Its effectiveness is demonstrated under various working conditions (variable final load, activity factor, supply voltage and process corner). Simulations based on a 45-nm technology showed that the tapered-VTH approach can provide a 3X energy reduction, at the parity of the delay, with respect to single-VTH design. This energy reduction was shown to be even greater (up to 4X) in presence of process variations (FF corner).

[1]  Kjell O. Jeppson,et al.  CMOS Circuit Speed and Buffer Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  C. Prunty,et al.  Optimum tapered buffer , 1992 .

[3]  S. R. Vemuru,et al.  Variable-taper CMOS buffers , 1991 .

[4]  K. Lee,et al.  Design of CMOS tapered buffer for minimum power-delay product , 1994, IEEE J. Solid State Circuits.

[5]  Eby G. Friedman,et al.  A unified design methodology for CMOS tapered buffers , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[6]  Hua Wang,et al.  Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Massimo Alioto,et al.  General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Yehea I. Ismail,et al.  Multiple Threshold Voltage Design Scheme for CMOS Tapered Buffers , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[9]  Massimo Alioto,et al.  Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[10]  A. Tuszynski,et al.  CMOS tapered buffer , 1990 .

[11]  Massimo Alioto,et al.  Power-Aware Design of Nanometer MCML Tapered Buffers , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.