The Weakest Memory-Access Order

Abstract In 1979 Lamport explained that a multiprocessor that allows out-of-order memory access may obtain incorrect results. In the present article, a conceptual framework is developed for understanding this problem, and the problem is defined in terms of this framework. Then the problem is solved in the weakest manner possible, and the weakest order is related to prior access-order solutions. At the heart of the underlying conceptual framework is a model of asynchronous multiprocess computation, which includes a model of asynchronous interprocess communication.

[1]  Gary L. Peterson,et al.  Myths About the Mutual Exclusion Problem , 1981, Inf. Process. Lett..

[2]  Abraham Silberschatz,et al.  Operating System Concepts , 1983 .

[3]  Philip Bitar,et al.  A Critique of Trace-Driven Simulation for Shared-Memory Multiprocessors , 1990 .

[4]  Edsger W. Dijkstra,et al.  Solution of a problem in concurrent programming control , 1965, CACM.

[5]  Michel Dubois,et al.  Memory Access Dependencies in Shared-Memory Multiprocessors , 1990, IEEE Trans. Software Eng..

[6]  Michel Cekleov,et al.  Formal Specification of Memory Models , 1992 .

[7]  Maurice Herlihy,et al.  Linearizability: a correctness condition for concurrent objects , 1990, TOPL.

[8]  Yehuda Afek,et al.  A lazy cache algorithm , 1989, SPAA '89.

[9]  Leslie Lamport,et al.  The mutual exclusion problem: part I—a theory of interprocess communication , 1986, JACM.

[10]  Alvin M. Despain,et al.  Multiprocessor cache synchronization: issues, innovations, evolution , 1986, ISCA 1986.

[11]  Erik Hagersten,et al.  Race-free interconnection networks and multiprocessor consistency , 1991, [1991] Proceedings. The 18th Annual International Symposium on Computer Architecture.

[12]  Olvi L. Mangasarian,et al.  Asynchronous parallel successive overrelaxation for the symmetric linear complementarity problem , 1988, Math. Program..

[13]  William W. Collier,et al.  Reasoning about parallel architectures , 1992 .

[14]  Leslie Lamport,et al.  Time, clocks, and the ordering of events in a distributed system , 1978, CACM.

[15]  Dennis Shasha,et al.  Efficient and correct execution of parallel programs that share memory , 1988, TOPL.

[16]  Carla Schlatter Ellis,et al.  An Example of Correct Global Trace Generation , 1992 .

[17]  Leslie Lamport,et al.  How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs , 2016, IEEE Transactions on Computers.

[18]  James R. Goodman,et al.  Cache Consistency and Sequential Consistency , 1991 .

[19]  Jayadev Misra Axioms for memory access in asynchronous hardware systems , 1986, TOPL.