Processor Pipelines and Static Worst-Case Execution Time Analysis

Worst-Case Execution Time (WCET) estimates for programs are necessary when building real-time systems. They are used to ensure timely responses from interrupts, to guarantee the throughput of cycli ...

[1]  Giuseppe Lipari,et al.  Minimizing memory utilization of real-time task sets in single and multi-processor systems-on-a-chip , 2001, Proceedings 22nd IEEE Real-Time Systems Symposium (RTSS 2001) (Cat. No.01PR1420).

[2]  J. Eyre,et al.  The digital signal processor Derby , 2001 .

[3]  David B. Whalley,et al.  Bounding loop iterations for timing analysis , 1998, Proceedings. Fourth IEEE Real-Time Technology and Applications Symposium (Cat. No.98TB100245).

[4]  Jörn Schneider,et al.  Pipeline behavior prediction for superscalar processors by abstract interpretation , 1999, LCTES '99.

[5]  Sang Lyul Min,et al.  Efficient worst case timing analysis of data caching , 1996, Proceedings Real-Time Technology and Applications.

[6]  Ron K. Cytron,et al.  Hashtables for Embedded and Real-Time Systems , 2001 .

[7]  Stefan M. Petters,et al.  Making worst case execution time analysis for hard real-time tasks on state of the art processors feasible , 1999, Proceedings Sixth International Conference on Real-Time Computing Systems and Applications. RTCSA'99 (Cat. No.PR00306).

[8]  Peter P. Puschner,et al.  Calculating the maximum execution time of real-time programs , 1989, Real-Time Systems.

[9]  Peter P. Puschner,et al.  Developing real-time tasks with predictable timing , 1992, IEEE Software.

[10]  Hewlett-Packard THE HP PA-8000 RISC CPU , 2022 .

[11]  Wang Yi,et al.  Uppaal in a nutshell , 1997, International Journal on Software Tools for Technology Transfer.

[12]  Rolf Ernst,et al.  Execution cost interval refinement in static software analysis , 2001, J. Syst. Archit..

[13]  Pradip Bose,et al.  Performance Analysis and Its Impact on Design , 1998, Computer.

[14]  Mendel Rosenblum,et al.  Using complete machine simulation to understand computer system behavior , 1998 .

[15]  Frank Müller,et al.  Timing Analysis for Instruction Caches , 2000, Real-Time Systems.

[16]  Guillem Bernat,et al.  WCET analysis of reusable portable code , 2001, Proceedings 13th Euromicro Conference on Real-Time Systems.

[17]  Sharad Malik,et al.  Cache modeling for real-time software: beyond direct mapped instruction caches , 1996, 17th IEEE Real-Time Systems Symposium.

[18]  Alexandre Yakovlev,et al.  Analysing superscalar processor architectures with coloured Petri nets , 1998, International Journal on Software Tools for Technology Transfer.

[19]  Jakob Engblom,et al.  Static Properties of Commercial Real-Time and Embedded Systems , 1998 .

[20]  Sang Lyul Min,et al.  A worst case timing analysis technique for multiple-issue machines , 1998, Proceedings 19th IEEE Real-Time Systems Symposium (Cat. No.98CB36279).

[21]  Doug Burger,et al.  Measuring Experimental Error in Microprocessor Simulation , 2001, ISCA 2001.

[22]  Isabelle Puaut,et al.  Worst Case Execution Time Analysis for a Processor with Branch Prediction , 2004, Real-Time Systems.

[23]  Anders Ive,et al.  Runtime performance evaluation of embedded software , 1998 .

[24]  Roderick Chapman,et al.  Static timing analysis and program proof , 1995 .

[25]  Bruce Jacob,et al.  The performance and energy consumption of three embedded real-time operating systems , 2001, CASES '01.

[26]  Peter M. Kogge,et al.  The Architecture of Pipelined Computers , 1981 .

[27]  Jakob Engblom,et al.  Why SpecInt95 should not be used to benchmark embedded systems tools , 1999, LCTES '99.

[28]  Yanhong A. Liu,et al.  Automatic Accurate Time-Bound Analysis for High-Level Languages , 1998, LCTES.

[29]  Raimund Kirner,et al.  Using Real Hardware to Create an Accurate Timing Model for Execution-Time Analysis , 2001 .

[30]  Jakob Engblom,et al.  Efficient longest executable path search for programs with complex flows and pipeline effects , 2001, CASES '01.

[31]  Frank Mueller,et al.  Timing Predictions for Multi-Level Caches , 1997 .

[32]  David B. Whalley,et al.  Bounding Pipeline and Instruction Cache Performance , 1999, IEEE Trans. Computers.

[33]  Yale N. Patt Requirements, bottlenecks, and good fortune: agents for microprocessor evolution , 2001 .

[34]  Joseph A. Fisher,et al.  Predicting conditional branch directions from previous runs of a program , 1992, ASPLOS V.

[35]  Jan Gustafsson Analyzing execution-time of object-oriented programs using abstract interpretation , 2000 .

[36]  David B. Whalley,et al.  Timing analysis for data caches and set-associative caches , 1997, Proceedings Third IEEE Real-Time Technology and Applications Symposium.

[37]  Rohit Jain,et al.  Variability in the execution of multimedia applications and implications for architecture , 2001, ISCA 2001.

[38]  Dick Price,et al.  Pentium FDIV flaw-lessons learned , 1995, IEEE Micro.

[39]  Thomas A. Henzinger,et al.  HYTECH: a model checker for hybrid systems , 1997, International Journal on Software Tools for Technology Transfer.

[40]  Neil C. Audsley,et al.  Predictable and efficient virtual addressing for safety-critical real-time systems , 2001, Proceedings 13th Euromicro Conference on Real-Time Systems.

[41]  Wolfgang A. Halang,et al.  On safety-critical computer control systems , 1997, Proceedings of Computer Based Medical Systems.

[42]  Per Stenström,et al.  Timing anomalies in dynamically scheduled microprocessors , 1999, Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054).

[43]  Stavros Tripakis,et al.  Kronos: A Model-Checking Tool for Real-Time Systems , 1998, CAV.

[44]  Alan Burns,et al.  Statistical analysis of WCET for scheduling , 2001, Proceedings 22nd IEEE Real-Time Systems Symposium (RTSS 2001) (Cat. No.01PR1420).

[45]  Erik R. Altman,et al.  Advances and future challenges in binary translation and optimization , 2001, Proc. IEEE.

[46]  Friedhelm Stappert,et al.  Predicting pipelining and caching behaviour of hard real-time programs , 1997, Proceedings Ninth Euromicro Workshop on Real Time Systems.

[47]  Jakob Engblom,et al.  Validating a Worst-Case Execution Time Analysis Method for an Embedded Processor , 2001 .

[48]  Sang Lyul Min,et al.  A worst case timing analysis technique for optimized programs , 1998, Proceedings Fifth International Conference on Real-Time Computing Systems and Applications (Cat. No.98EX236).

[49]  Jakob Engblom,et al.  Worst-Case Execution Time Analysis for Optimized Code , 1997 .

[50]  David B. Whalley,et al.  Supporting Timing Analysis by Automatic Bounding of Loop Iterations , 2000, Real-Time Systems.

[51]  Corporate Motorola MC88200 Cache-Memory Management Unit User's Manual , 1989 .

[52]  Raimund Kirner,et al.  Transformation of path information for WCET analysis during compilation , 2001, Proceedings 13th Euromicro Conference on Real-Time Systems.

[53]  Iain Bate,et al.  Low-level analysis of a portable Java byte code WCET analysis framework , 2000, Proceedings Seventh International Conference on Real-Time Computing Systems and Applications.

[54]  James W. Layland,et al.  Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment , 1989, JACM.

[55]  David Brunton Stewart Twenty-Five Most Common Mistakes with Real-Time Software Development , 1999 .

[56]  Jakob Engblom,et al.  A Worst-Case Execution-Time Analysis Tool Prototype for Embedded Real-Time Systems , 2001 .

[57]  Valérie Bertin,et al.  Towards validated real-time software , 2000, Proceedings 12th Euromicro Conference on Real-Time Systems. Euromicro RTS 2000.

[58]  Todd M. Austin,et al.  SimpleScalar: An Infrastructure for Computer System Modeling , 2002, Computer.

[59]  Jakob Engblom,et al.  Structured Testing of Worst-Case Execution Time Analysis Methods , 2000 .

[60]  Jakob Engblom,et al.  Pipeline timing analysis using a trace-driven simulator , 1999, Proceedings Sixth International Conference on Real-Time Computing Systems and Applications. RTCSA'99 (Cat. No.PR00306).

[61]  Rolf Ernst,et al.  Interval-Based Analysis of Software Processes , 2001, OM '01.

[62]  Jan Gustafsson,et al.  Towards Industry-Strength Worst-Case Execution Time Analysis , 1999 .

[63]  Henrik Theiling,et al.  Run-Time Guarantees for Real-Time Systems - The USES Approach , 1999, GI Jahrestagung.

[64]  Rolf Ernst,et al.  Embedded program timing analysis based on path clustering and architecture classification , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[65]  Carl von Platen,et al.  Storage allocation for embedded processors , 2001, CASES '01.

[66]  Roland Lang,et al.  WCET Analysis for Systems Modelled in Matlab/Simulink ∗† , 2001 .

[67]  Per Stenström,et al.  An Integrated Path and Timing Analysis Method based on Cycle-Level Symbolic Execution , 1999, Real-Time Systems.

[68]  John Paul Shen,et al.  Calibration of Microprocessor Performance Models , 1998, Computer.

[69]  Jakob Engblom Static properties of commercial embedded real-time programs, and their implication for worst-case execution time analysis , 1999, Proceedings of the Fifth IEEE Real-Time Technology and Applications Symposium.

[70]  Christopher J. Hughes,et al.  RSIM: Simulating Shared-Memory Multiprocessors with ILP Processors , 2002, Computer.

[71]  David B. Whalley,et al.  Parametric Timing Analysis , 2001, OM '01.

[72]  Alan C. Shaw,et al.  Experiments with a program timing tool based on source-level timing schema , 1990, [1990] Proceedings 11th Real-Time Systems Symposium.

[73]  Isabelle Puaut,et al.  Worst-case execution time analysis of the RTEMS real-time operating system , 2001, Proceedings 13th Euromicro Conference on Real-Time Systems.

[74]  Rajeev Barua,et al.  Heterogeneous memory management for embedded systems , 2001, CASES '01.

[75]  Jason R. C. Patterson,et al.  Accurate static branch prediction by value range propagation , 1995, PLDI '95.

[76]  Sharad Malik,et al.  Performance Analysis of Embedded Software Using Implicit Path Enumeration , 1995, 32nd Design Automation Conference.

[77]  Per Stenström,et al.  Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques , 1998, LCTES.

[78]  Veikko Seppänen,et al.  Strategic needs and future trends of embedded software , 1997 .

[79]  Henrik Theiling,et al.  Combining abstract interpretation and ILP for microarchitecture modelling and program path analysis , 1998, Proceedings 19th IEEE Real-Time Systems Symposium (Cat. No.98CB36279).

[80]  Stavros Tripakis,et al.  KRONOS: A Model-Checking Tool for Real-Time Systems (Tool-Presentation for FTRTFT '98) , 1998, FTRTFT.

[81]  David B. Whalley,et al.  Tighter timing predictions by automatic detection and exploitation of value-dependent constraints , 1999, Proceedings of the Fifth IEEE Real-Time Technology and Applications Symposium.

[82]  Henrik Theiling,et al.  Reliable and Precise WCET Determination for a Real-Life Processor , 2001, EMSOFT.

[83]  Isabelle Puaut,et al.  A modular and retargetable framework for tree-based WCET analysis , 2001, Proceedings 13th Euromicro Conference on Real-Time Systems.

[84]  John Paul Shen,et al.  System-level issues for software thread integration: guest triggering and host selection , 1999, Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054).

[85]  Christopher M. Collins,et al.  An Evaluation of Embedded System Behavior Using Full-System Software Emulation , 2000 .

[86]  Guang R. Gao,et al.  Identifying loops using DJ graphs , 1996, TOPL.

[87]  Jan Gustafsson,et al.  Deriving Annotations for Tight Calculation of Execution Time , 1997, Euro-Par.

[88]  Sang Lyul Min,et al.  Analysis of the impacts of overestimation sources on the accuracy of worst case timing analysis , 1999, Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054).

[89]  Junqiang Sun,et al.  Tms320c6000 cpu and instruction set reference guide , 2000 .

[90]  Sang Lyul Min,et al.  An Accurate Worst Case Timing Analysis for RISC Processors , 1995, IEEE Trans. Software Eng..

[91]  Jakob Engblom,et al.  Comparing Different Worst-Case Execution Time Analysis Methods , 2000 .

[92]  Sven Montan Validation of Cycle-Accurate CPU Simulators against Real Hardware , 2001 .

[93]  Alan Burns,et al.  Predicting computation time for advanced processor architectures , 2000, Proceedings 12th Euromicro Conference on Real-Time Systems. Euromicro RTS 2000.

[94]  Friedhelm Stappert,et al.  Complete worst-case execution time analysis of straight-line hard real-time programs , 2000, J. Syst. Archit..

[95]  Peter Altenbernd,et al.  On the false path problem in hard real-time programs , 1996, Proceedings of the Eighth Euromicro Workshop on Real-Time Systems.

[96]  Niklas Holsti,et al.  USING A WORST-CASE EXECUTION TIME TOOL FOR REAL-TIME VERIFICATION OF THE DEBIE SOFTWARE , 2000 .

[97]  G. Ramalingam,et al.  On loops, dominators, and dominance frontier , 2000, PLDI '00.

[98]  Greger Ottosson,et al.  Worst-case execution time analysis for modern hardware architectures , 1997 .

[99]  Jim Handy,et al.  The cache memory book , 1993 .

[100]  Stefan M. Petters Bounding the execution time of real-time tasks on modern processors , 2000, Proceedings Seventh International Conference on Real-Time Computing Systems and Applications.

[101]  Péter Kacsuk,et al.  Advanced computer architectures - a design space approach , 1997, International computer science series.

[102]  Jakob Engblom,et al.  Modeling complex flows for worst-case execution time analysis , 2000, Proceedings 21st IEEE Real-Time Systems Symposium.

[103]  Niklas Holsti,et al.  Worst-case execution time analysis for digital signal processors , 2000, 2000 10th European Signal Processing Conference.

[104]  Alfred V. Aho,et al.  Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.

[105]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[106]  Donal Heffernan,et al.  Expanding Automotive Electronic Systems , 2002, Computer.