Timing analysis and optimization of a high-performance CMOS processor chipset

We describe the timing analysis and optimization methodology used for the chipset inside the IBM S/390 Parallel Enterprise Server-Generation 3. After an introduction to the concepts of static timing analysis, we describe the timing-modeling for the gates and interconnects, explain the optimization schemes and present obtained results.

[1]  Olivier Coudert,et al.  Gate sizing: a general purpose optimization approach , 1996, Proceedings ED&TC European Design and Test Conference.

[2]  Lawrence T. Pileggi,et al.  A Gate-Delay Model for High-Speed CMOS Circuits , 1994, 31st Design Automation Conference.

[3]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[5]  Lawrence T. Pileggi,et al.  RICE: rapid interconnect circuit evaluator , 1991, 28th ACM/IEEE Design Automation Conference.

[6]  Krishna P. Belkhale,et al.  Timing analysis with known false sub graphs , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[7]  Vasant B. Rao,et al.  Delay Analysis of the Distributed RC Line , 1995, 32nd Design Automation Conference.

[8]  Jürgen Koehl,et al.  A flat, timing-driven design system for a high-performance CMOS processor chipset , 1998, Proceedings Design, Automation and Test in Europe.

[9]  Olivier Coudert,et al.  New algorithms for gate sizing: a comparative study , 1996, DAC '96.

[10]  Lawrence T. Pileggi,et al.  Modeling the "Effective capacitance" for the RC interconnect of CMOS gates , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Jens Vygen,et al.  Algorithms for large-scale flat placement , 1997, DAC.