Method and apparatus for monitoring an electronic processing unit

The invention concerns a method and device for monitoring a computing unit as used in control devices for instance. The monitoring device generates a reset signal if the supply voltage drops below a given level below which a defined operation can no longer be guaranteed. When a reset signal occurs, a predefined code is compared with the contents of a volatile memory and, as a result of the comparison, a signal produced which determines the subsequent operating sequence. The optimum subsequent operating sequence is determined rapidly and reliably by virtue of the fact that, if the contents of the volatile memory are the same as the code, the operating conditions existing at the time the reset signal occurred are maintained by means of the control unit while, if the contents of the volatile memory differ from the code, another initialization is carried out.