14.7 A 10GHz TCP Offload Accelerator for 10Gb/s Ethernet in 90nm Dual-VT CMOS

[1]  Vivek De,et al.  Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[2]  James Tschanz,et al.  Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors , 2001, ISLPED '01.

[3]  Vern Paxson,et al.  End-to-end Internet packet dynamics , 1997, SIGCOMM '97.

[4]  H. Salwen,et al.  An analysis of TCP processing overhead , 1989, Proceedings [1988] 13th Conference on Local Computer Networks.