Variation Aware Routing for Three-Dimensional FPGAs

To maximize the potential of three-dimensional integrated circuit architectures, 3D CAD tools must be developed that are on-par with their 2D counterparts. In this paper, we present a statistical static timing analysis (SSTA) engine designed to deal with both the uncorrelated and correlated variations in 3D FPGAs. We consider the effects of intra-die and inter-die variation. Using the 3D physical design tool TPR as a base, we develop a new 3D routing algorithm which improves the average performance of two layer designs by over 22% and three layer designs by over 27%. To the best of our knowledge, this is the first physical design tool to consider variation in the routing and timing analysis of 3D FPGAs.

[1]  Sachin S. Sapatnekar,et al.  Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal , 2003, ICCAD 2003.

[2]  Anantha Chandrakasan,et al.  Models of Process Variations in Device and Interconnect , 2001 .

[3]  Gao Hai-Xia.  Circuit Design of FPGA Routing Switches , 2003 .

[4]  Kia Bazargan,et al.  Three-dimensional place and route for FPGAs , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[5]  Mingjie Lin,et al.  Performance Benefits of Monolithically Stacked 3-D FPGA , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[7]  John E. Karro,et al.  Placement and Routing for Three-Dimensional FPGAs , 1996 .

[8]  Sani R. Nassif,et al.  Models of process variations in device and interconnect , 2000 .

[9]  Guy Lemieux,et al.  Circuit design of routing switches , 2002, FPGA '02.

[10]  James P. Cohoon,et al.  A Spiffy tool for the simultaneous placement and global routing for three-dimensional field-programmable gate arrays , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[11]  Deming Chen,et al.  FastYield: Variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization , 2009, 2009 Asia and South Pacific Design Automation Conference.

[12]  Jinjun Xiong,et al.  Robust Extraction of Spatial Correlation , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[15]  Edmund J. Sprogis,et al.  Wafer-level 3D integration technology , 2008, IBM J. Res. Dev..

[16]  Yan Lin,et al.  Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Katsuyuki Sakuma,et al.  Three-dimensional silicon integration , 2008, IBM J. Res. Dev..

[18]  Kia Bazargan,et al.  Variation-aware routing for FPGAs , 2007, FPGA '07.

[19]  David Blaauw,et al.  Statistical estimation of leakage current considering inter- and intra-die process variation , 2003, ISLPED '03.

[20]  Mahmut T. Kandemir,et al.  Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  D. Sylvester,et al.  Statistical estimation of leakage current considering inter- and intra-die process variation , 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..