Robust Hybrid TFET-MOSFET Circuits in Presence of Process Variations and Soft Errors

In this work, to improve the timing yield of Tunnel Field Effect Transistor (TFET) circuits in the presence of process variations as well as their soft-error resiliency, we propose replacing some of TFET-based gates by MOSFET-based ones. The effectiveness of the proposed TFET-MOSFET hybrid implementation of the circuits are investigated by first studying the impacts of the process variation on the performances (I-V characteristics) of both homojunction InAs TFETs and MOSFETs. Next, to analyze the soft error rate of the circuits, the particle hit-induced transient current profiles of these devices are extracted. Based on these studies, a hybrid TFET-MOSFET circuit design approach which improves the reliability and soft-error resiliency compared to those of pure TFET-based circuits is suggested. Finally, the efficacy of the design approach is investigated by applying it to some circuits of ISCAS’89 benchmark package.

[1]  Massoud Pedram,et al.  Study on the impact of device parameter variations on performance of III-V homojunction and heterojunction tunnel FETs , 2016 .

[2]  Yong-Bin Kim,et al.  Soft-Error Hardening Designs of Nanoscale CMOS Latches , 2009, 2009 27th IEEE VLSI Test Symposium.

[3]  Takashi Matsukawa,et al.  Variation behavior of tunnel-FETs originated from dopant concentration at source region and channel edge configuration , 2014, 2014 44th European Solid State Device Research Conference (ESSDERC).

[4]  Massoud Pedram,et al.  Hybrid TFET-MOSFET circuits: An approach to design reliable ultra-low power circuits in the presence of process variation , 2016, 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

[5]  Huichu Liu,et al.  Technology assessment of Si and III-V FinFETs and III-V tunnel FETs from soft error rate perspective , 2012, 2012 International Electron Devices Meeting.

[6]  Manisha Pattanaik,et al.  Parameter variation aware hybrid TFET-CMOS based power gating technique with a temperature variation tolerant sleep mode , 2014, Microelectron. J..

[7]  M. Chan,et al.  The impact of device parameter variation on double gate tunneling FET and double gate MOSFET , 2010, 2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC).

[8]  Sung Hwan Kim,et al.  Study of Random Dopant Fluctuation Effects in Germanium-Source Tunnel FETs , 2011, IEEE Transactions on Electron Devices.

[9]  Narayanan Vijaykrishnan,et al.  Ultra Low Power Circuit Design Using Tunnel FETs , 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

[10]  Abhijit Chatterjee,et al.  Soft-error tolerance analysis and optimization of nanometer circuits , 2005, Design, Automation and Test in Europe.

[11]  Ching-Te Chuang,et al.  Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits , 2014, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[12]  Ahmet Tura.  Novel Vertical Tunnel Transistors for Continued Voltage Scaling , 2010 .

[13]  Xueqing Li,et al.  Enabling Power-Efficient Designs with III-V Tunnel FETs , 2014, 2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS).

[14]  Narayanan Vijaykrishnan,et al.  Evaluation of tunnel FET-based flip-flop designs for low power, high performance applications , 2013, International Symposium on Quality Electronic Design (ISQED).

[15]  Diana Marculescu,et al.  Modeling and Optimization for Soft-Error Reliability of Sequential Circuits , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Narayanan Vijaykrishnan,et al.  Tunnel FET technology: A reliability perspective , 2014, Microelectron. Reliab..

[17]  Mehdi Kamal,et al.  Hybrid TFET-MOSFET circuit: A solution to design soft-error resilient ultra-low power digital circuit , 2017, Integr..