Integration of a Double Polysilican, Fully Self-Aligned Bipolar Transistor into a 0 .5p1 BiCMOS Technology for Fast 4MBit SRAMs
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Hayden | Á. | J. | Y. See | V. Kaushik | F. Walczyk | T. Mele | J. Burnett | C. Lage | Perera | J.
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